Learn pending frame throttle
Assignee3Com Corporation
InventorsDavid S. Miller, Lawrence Aaron Boxer, Edward A. Heiner, Jr.
Life of this patent
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Abstract
Flow of data units to an address resolution processor is controlled to inhibit multiple data units from a single multicast flow from being enqueued with the address resolution processor. In a switch having a plurality of Input/Output Application Specific Integrated Circuits (“I/O ASICs”) with a plurality of ports, no more than one data unit from each I/O ASIC is permitted to be enqueued with the address resolution processor at any point in time. A separate learn pending indicator may be defined for each I/O ASIC in the switch.
Claims12
A method for updating an address table in a network switch having an address resolution processor operative to facilitate an address learning operation by transmitting new address information to segments of a distributed address table and at least one input/output circuit that includes at least one port, comprising the steps of:
- receiving a multicast data unit associated with a first multicast flow in one of said at least one output port of said input/output circuit;
- searching in the address table for an entry that is pertinent to the multicast data unit;
- determining whether an address learning operation is pending for the first flow at the address resolution processor;
- and
- if a pertinent entry is not located in said searching step and an address learning operation is not pending for the first flow at the address resolution processor, enqueueing at least a portion of the data unit with the address resolution processor to initiate an address learning operation.
A switch for facilitating transmission of multicast and unicast data units in a computer network, comprising:
- a switch fabric;
- a plurality of input/output circuits that are coupled to said switch fabric, each input/output circuit having a segment of a distributed address memory and at least one port through which data units are received;
- an address resolution processor operative to derive address information from a multicast data unit enqueued with said address resolution processor and to distribute said address information to said address memory segments;
- and
- a separate learn pending indicator for each input/output circuit that indicates whether a multicast data unit is enqueued with said address resolution processor from that input/output circuit, wherein a multicast data unit received by one of said input/output circuits is not forwarded to said address resolution processor if said learn pending indicator for that input/output circuit indicates that a multicast data unit is enqueued with said address resolution processor.
Dependencies are inferred from the claim text.