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US 6,310,826 B2Granted
Semiconductor device having a test circuit
AssigneeFujitsu Limited
InventorTomohiko Koto
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a memory circuit from which data is read in correspondence with a first reference clock signal. A multiplexer outputs the data read from the memory circuit in correspondence with the second reference clock signal. A comparison determination circuit receives the data read from the memory circuit via the multiplexer and compares the read data with an expected data value in correspondence with the second reference clock signal to generate determination result data.
Claims12
A semiconductor device comprising:
- an internal circuit for generating data;
- an I/O circuit for receiving the data and outputting output data in correspondence with a rising edge and a falling edge of a reference clock signal;
- and
- a comparison determination circuit for receiving the output data, comparing the output data with an expected data value, and generating determination result data in correspondence with the rising edge and the falling edge of the reference clock signal.
1 more element
A semiconductor device comprising:
- an internal circuit for generating data in correspondence with a first reference clock signal;
- an I/O circuit for receiving the data and outputting output data in correspondence with a rising edge and a falling edge of a second reference clock signal;
- and
- a comparison determination circuit for receiving the output data, comparing the output data with an expected data value, and generating determination result data in correspondence with the rising edge and the falling edge of the second reference clock signal.
1 more element
Dependencies are inferred from the claim text.