Data writing method for semiconductor memory device
AssigneeFujitsu Limited
InventorTakaaki Furuyama
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a control circuit that sets read and write latency periods such that the write data input circuit is activated and acquires the write data after the receipt of a write command and upon the lapse of the write latency period. The write latency period of the memory device is set to be one latency value less than the read latency period.
Claims12
A method for writing data to a semiconductor memory device using an input circuit for write data, comprising the steps of:
- supplying a word line activation command to the semiconductor memory device;
- supplying a write command to the semiconductor memory device after the lapse of a first predetermined latency period according to a clock signal after the supply of the word line activation command;
- activating the input circuit in response to the write command;
- acquiring the write data after the lapse of a write latency period after activation of the input circuit;
- and
- performing a write operation of the write data supplied to the input circuit, wherein the first predetermined latency period is decreased when the write latency period is increased.
A method for writing data to a semiconductor memory device using an input circuit for write data, wherein the semiconductor memory device outputs written data upon the lapse of a read latency period after a read command has been supplied thereto, the method comprising the steps of:
- supplying a word line activation command to the semiconductor memory device;
- supplying a write command to the semiconductor memory device after the lapse of a first predetermined latency period according to a clock signal after the supply of the word line activation command;
- activating the input circuit in response to the write command;
- acquiring the write data after the lapse of a write latency period after the write command has been supplied to the input circuit;
- and
- performing a write operation of the write data supplied to the input circuit, wherein the write latency period is shorter than the read latency period, and wherein the first predetermined latency period is decreased when the write latency period is increased.
A semiconductor memory device, comprising:
- a first input circuit that acquires a write command in accordance with a clock signal;
- a second input circuit that acquires write data in accordance with the clock signal;
- a write latency setting circuit connected to the first input circuit for setting a write latency period in accordance with the clock signal;
- and
- a control circuit connected to the first and second input circuits for activating the second input circuit in response to the write command to acquire the write data after the lapse of the write latency period, wherein the write latency period is set so that the second input circuit surely acquires the write data after the activation of the second input circuit.
A semiconductor memory device, comprising:
- a first input circuit that acquires an address signal in accordance with a clock signal;
- a second input circuit that acquires various commands including a write command in accordance with the clock signal;
- a third input circuit that acquires write data in accordance with the clock signal;
- a write latency setting circuit connected to the second and third input circuits for setting a write latency period in accordance with the clock signal;
- and
- a control circuit connected to the second and third input circuits for activating the third input circuit in response to the write command to acquire the write data after the lapse of the write latency period after the second input circuit has acquired the write command, wherein the write latency period is set so that the third input circuit surely acquires the write data after the activation of the third input circuit.
Dependencies are inferred from the claim text.