Integrated memory with two burst operation types

An integrated memory, comprising:

• address inputs for feeding in external column addresses having a least significant address bit, a second least significant address bit, and a third least significant address bit;
• a first column decoder for selecting first column select lines and a second column decoder for selecting second column select lines, each of said column decoders having first and second inputs for feeding in internal column addresses derived from the external column addresses;
• a bidirectional address counting unit, said address counting unit:
• receiving at least a second and a third least significant address bit of one of the external column addresses as a start address in a first burst operating mode and in a second burst operating mode;
• performing a counting step in each case for generating partial addresses of a plurality of the internal column addresses, proceeding from the start address;
• and
• having a first counting direction in the first burst operating mode in the case of a first logic state of the second least significant address bit, and a second counting direction in other cases;
• wherein those address bits of the external column address that are not fed to said address counting unit, except the least significant address bit, are fed to said first inputs of said two column decoders;
• said address counting unit, for transferring the partial addresses generated thereby, having an output connected to said second inputs of said first column decoder and, via a transformation unit, to said second inputs of said second column decoder;
• said transformation unit incrementing the partial address generated by said address counting unit by a specific value in the second burst operating mode in the case of a first logic state of the least significant address bit of the external column address and, in the other cases, forwarding the partial address unchanged to said second inputs of said second column decoder.