Circuit for generating internal column strobe signal in synchronous semiconductor memory device

A circuit for generating internal column strobe signal in a synchronous semiconductor memory device, comprising:

• a clock buffer part for buffering an external clock signal to generate a first internal clock signal;
• an internal clock generation part for receiving the first internal clock signal to generate a second internal clock signal;
• a command decoder part for periodically generating an external column strobe enable signal synchronized to the second internal clock signal by a chip select bar signal, a row address strobe bar signal, a column address strobe bar signal and a write enable bar signal;
• a burst signal generation part for a burst signal generated by the external column strobe enable signal and disabled by a burst length stop signal;
• and
• an internal column strobe generation part being controlled by the chip select bar signal, the row address bar signal, the column address bar signal, and the write enable bar signal, for generating an internal column strobe signal synchronized to the second internal clock signal inputted after the burst signal is enabled, and for stopping the generation of the internal column strobe signal by the disablement of the burst signal.