Delay locking high speed clock synchronization method and circuit

A clock synchronizer circuit to provide an internal clock signal for an integrated circuit that is synchronized to an external system clock signal, such that said internal clock signal is aligned with and has minimal skew from said external system clock signal, whereby said clock synchronizer circuit is comprising:

• a frequency divider means that receives said external system clock signal and divides its frequency by a dividing factor to form a divided external clock signal;
• a plurality of serially connected delaying means, whereby a first delaying means is connected to the frequency divider means to receive the divided external clock signal, and each delaying means delays said delayed external clock signal by an incremental period of delay to form a plurality of delayed and divided external clock signals;
• a plurality of clock synchronization delay means, whereby a first clock synchronization delay means is connected to frequency divider means and each remaining clock synchronization delay means is connected to one of the plurality of serially connected delaying means to synchronize each delayed and divided external clock signal to the external system clock signal;
• and
• a logical combining means to combine the synchronized, delayed and divided external clock signals to form said internal clock signal.

A synchronous dynamic random access memory to retain digital data, comprising:

• a clock generator circuit connected between an external system clock distribution circuit and a plurality of banks of arrays of memory cells, an address circuit, a command circuit, a data control circuit, and a data input/output buffer to provide an internal clock signal to synchronize operation of said synchronous dynamic random access memory, whereby certain operations must occur in time with minimal deviation from said an external system clock signal and whereby said clock generator includes at least one clock synchronizer circuit, comprising;
• a plurality of serially connected delaying means to receive said external system clock signal and delay said external system clock signal by an incremental period of delay;
• a plurality of frequency divider means, whereby a first frequency divider means receives said external system clock signal and divides a frequency of said external system clock signal by a dividing factor and each remaining frequency divider means is connected to an output of one of the serially connected delaying means to divide a delayed external system clock signal by said dividing factor providing a plurality of divided external system clock signals;
• a plurality of clock synchronization delay means, whereby each clock synchronization delay means is connected to one of the plurality of frequency divider means to synchronized each divided external system clock signal to the external system clock signal;
• and
• a logical combining means to combine the synchronized, divided external system clock signal to form said internal clock signal.

A synchronous dynamic random access memory to retain digital data, comprising:

• a clock generator circuit connected between an external system clock distribution circuit and a plurality of banks of arrays of memory cells, an address circuit, a command circuit, a data control circuit, and a data input/output buffer to provide an internal clock signal to synchronize operation of said synchronous dynamic random access memory, whereby certain operations must occur in time with minimal deviation from said an external system clock signal and whereby said clock generator includes at least one clock synchronizer circuit, comprising;
• a frequency divider means that receives said external system clock signal and divides its frequency by a dividing factor to form a divided external clock signal;
• a plurality of serially connected delaying means, whereby a first delaying means is connected to the frequency divider means to receive the divided external clock signal, and each delaying means delays said delayed external clock signal by an incremental period of delay to form a plurality of delayed and divided external clock signals.;
• a plurality of clock synchronization delay means, whereby a first clock synchronization delay means is connected to frequency divider means and each remaining clock synchronization delay means is connected to one of the plurality of serially connected delaying means to synchronize each delayed and divided external clock signal to the external system clock signal;
• and
• a logical combining means to combine the synchronized, delayed and divided external clock signals to form said internal clock signal.

A method for generating an internal clock signal for an integrated circuit that is synchronized to an external system clock, such that said internal clock signal is aligned with and has minimal skew from said external system clock signal whereby said method is comprising the steps of:

• acquiring said external system clock signal;
• generating a plurality of delayed, submultiple clock signals;
• synchronizing by delaying each of said plurality of delayed submultiple clock signals to the external system clock to form a plurality of synchronized submultiple clocks;
• and
• logically combining said plurality of synchronized submultiple clocks to form the internal clock.