Clock-synchronous semiconductor memory device and access method thereof

A semiconductor device comprising:

• a memory cell array having a plurality of memory cells arranged in rows and columns;
• a first circuit for receiving an address signal and designating a memory cell in said memory cell array;
• a second circuit for inputting data into a memory cell selected by said first circuit and outputting the data from the memory cell selected by said specification section;
• a third circuit for receiving a clock signal and counting a number of clock cycles of said clock signal;
• and
• a fourth circuit for receiving an output signal of said third circuit and a first control signal, for outputting a plurality of said data in synchronism with said clock signal after said first control signal is asserted, a beginning of an output of said data being determined by the output signal of said third circuit;
• wherein, whenever said first control signal is transitioned, said fourth circuit outputs from said second circuit data of the number of clock cycles determined according to the output signal from said third circuit and, output of said plurality of data is interrupted and data of another new group selected by said first circuit is continuously output from said second circuit.

A semiconductor device, comprising:

• a memory cell array having a plurality of memory cells arranged in rows and columns;
• a specification section for receiving an address signal and designating a memory cell in said memory cell array;
• a data input/output section for inputting data into a memory cell selected by said specification section and outputting the data from the memory cell selected by said specification section;
• a counting section for receiving a clock signal and counting a number of clock cycles of said clock signal;
• and
• a control section for receiving an output signal of said counting section and a first control signal, for outputting a plurality of said data in synchronism with said clock signal after said first control signal is asserted, a beginning of an output of said data being determined by an output signal of said counting section;
• wherein whenever said second control signal is transitioned, said control section outputs from said data input/output section data of the number of clock cycles determined according to the output signal from said counting section and, output of said plurality of data is interrupted and data of another new group selected by said specification section is continuously output from said data input/output section.

A semiconductor device, comprising;

• a memory cell array having a plurality of memory cells arranged in rows and columns;
• a first circuit for receiving an address signal and designating a memory cell in said memory cell array;
• a second circuit for inputting data into a memory cell selected by said first circuit and outputting the data from the memory cell selected by said first circuit;
• a third circuit for receiving a clock signal and counting a number of clock cycles of said clock signal;
• and
• a fourth circuit for receiving an output signal of said third circuit, a first control signal and a second control signal, for outputting a plurality of said data in synchronism with said clock signal after said second control signal is asserted, a beginning of an output of said data being determined by an output signal of said third circuit;
• wherein, whenever said second control signal is deasserted, said fourth circuit outputs from said second circuit data of the number of clock cycles determined according to the output signal from said third circuit and, output of said plurality of data is interrupted and data of another new group selected by said first circuit is continuously output from said second circuit.

A method for controlling a clock synchronous DRAM, comprising the steps of:

• supplying a basic clock signal and an address signal to said clock synchronous DRAM;
• and
• obtaining a plurality of output data output from the clock synchronous DRAM in synchronism with said basic clock signal after said address signal is asserted, output of said data beginning a number of clock cycles N (latency N, N being a positive integer ≧2) of said basic clock signals after said address signal is asserted, a different one of said data being output at each of said clock cycles after said output begins until said plurality of data is output,
• wherein said latency N is determined by a latency control signal supplied to the clock synchronous DRAM.