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US 6,310,820 B1Granted
Relaxed write timing for a memory device
AssigneeMicron Technology, Inc.
InventorsJohn D. Porter, William N. Thompson, Larren G. Weber
Life of this patent
Estimating the term…
Abstract
A memory device provides a relaxed write timing scheme that improves access time. The address and/or the data is set up to the memory array during a previous write cycle so that the next write cycle can proceed without delays produced in delivering the address and/or the data to the array during the write cycle in which the data is to be written to the array.
Claims30
A method of accessing a memory array of a memory device, the method comprising the acts of:
- (a) transferring an address into the memory device during a first write cycle;
- (b) transferring data into the memory device during a second write cycle;
- and
- (c) delivering the address and the data to the memory array during a third write cycle, wherein the first write cycle, the second write cycle, and the third write cycle are distinct from one another and performed sequentially.
1 more element
A method of accessing a memory array of a memory device, the method comprising the steps of:
- (a) setting up an address for delivery to the memory array during a first and a second write cycle;
- (b) setting up data for delivery to the memory array during the second write cycle;
- and
- (c) delivering the address and data to the memory array during a third write cycle, wherein the first write cycle, the second write cycle, and the third write cycle are distinct from one another and performed sequentially.
1 more element
A method of accessing a memory array of a memory device, the method comprising the acts of:
- (a) storing an address in a first address register in response to a first signal during a first write cycle;
- (b) transferring the address from the first address register to a second address register in response to a second signal during a second write cycle;
- (c) transferring the address from the second address register to a third address register in response to a third signal during a third write cycle;
- and
- (d) delivering the address from the third address register to the memory array in response to a fourth signal during the third write cycle, wherein the first write cycle, the second write cycle, and the third write cycle are distinct from one another and performed sequentially.
2 more elements
A method of accessing a memory array of a memory device, the method comprising the acts of:
- (a) storing data in a first data register in response to a first signal during a first write cycle;
- (b) transferring the data from a first data register to a second data register in response to a second signal during a second write cycle;
- and
- (c) during a third write cycle, transferring the data from the second data register to a write driver in response to a third signal, the write driver delivering the data to the memory array, wherein the first write cycle, the second write cycle, and the third write cycle are distinct from one another and performed sequentially.
1 more element
A method of accessing a memory array of a memory device, the method comprising the steps of:
- (a) storing an address in a first address register in response to a system clock signal;
- (b) transferring the address from the first address register to a second address register in response to a first write signal;
- (c) transferring the address from the second address register to a third address register in response to an end-of-write signal;
- (d) delivering the address from the third address register to the memory array in response to a write pulse signal;
- (e) storing data in a first data register in response to a second write signal;
- (f) transferring the data from a first data register to a second data register in response to the end-of-write signal;
- and
- (g) transferring the data from the second data register to a write driver in response to the write pulse signal, the write driver delivering the data to the memory array, wherein steps (a) through (g) are completed during three write cycles, wherein the three write cycles are distinct from one another and performed sequentially.
5 more elements
A method of accessing a memory array of a memory device, the method comprising the steps of:
- (a) storing an address in a first address register in response to a system clock signal;
- (b) transferring the address from the first address register to a second address register in response to a first write signal;
- (c) transferring the address from the second address register to a third address register in response to the next first write signal;
- (d) delivering the address from the third address register to the memory array in response to a write pulse signal;
- (e) storing data in a first data register in response to a second write signal;
- (f) transferring the data from a first data register to a second data register in response to an end-of-write signal;
- and
- (g) transferring the data from the second data register to a write driver in response to the write pulse signal. the write driver delivering the data to the memory array, wherein steps (a) through (g) are completed during three write cycles, wherein the three write cycles are distinct from one another and performed sequentially.
5 more elements
A method of accessing a memory array of a memory device, the method comprising the steps of:
- (a) storing an address in a first address register in response to a system clock signal;
- (b) transferring the address from the first address register to a second address register in response to a first write signal;
- (c) transferring the address from the second address register to a third address register in response to an end-of-write signal;
- (d) delivering the address from the third address register to the memory array in response to a write pulse signal;
- (e) storing data in a first data register in response to a second write signal;
- (f) transferring the data from a first data register to a second data register in response to the next second write signal;
- and
- (g) transferring the data from the second data register to a write driver in response to the write pulse signal, the write driver delivering the data to the memory array, wherein steps (a) through (g) are completed during three write cycles, wherein the three write cycles are distinct from one another and performed sequentially.
5 more elements
A method of accessing a memory array of a memory device, the method comprising the steps of:
- (a) generating a first write clock signal and a second write clock signal in response to a system clock signal and a write signal;
- (b) generating a write pulse signal in response to the first write clock signal;
- (c) generating an end-of-write signal in response to the first write clock signal and the write pulse signal;
- (d) storing an address in a first address register in response to the system clock signal;
- (e) transferring the address from the first address register to a second address register in response to the first write clock signal;
- (f) transferring the address from the second address register to a third address register in response to one of the end-of-write signal and the next first write clock signal;
- (g) delivering the address from the third address register to the memory array in response to the write pulse signal;
- (h) storing data in a first data register in response to the second write clock signal;
- (i) transferring the data from the first data register to a second address register in response to one of the end-of-write signal and the next second write clock signal;
- and
- (j) transferring the data from the second address register to a write driver in response to the write pulse signal, the write driver delivering the data to the memory array.
8 more elements
A method of accessing a memory array of a memory device, the method comprising the steps of:
- (a) generating a first write clock signal and a second write clock signal in response to a system clock signal and a write signal;
- (b) generating a write pulse signal in response to the first write clock signal;
- (c) generating an end-of-write signal in response to the first write clock signal and the write pulse signal;
- (d) storing an address in a first address register in response to the system clock signal;
- (e) transferring the address from the first address register to a second address register in response to the first write clock signal;
- (f) transferring the address from the second address register to a third address register in response to the end-of-write signal;
- (g) delivering the address from the third address register to the memory array in response to the write pulse signal;
- (h) storing data in a first data register in response to the second write clock signal;
- (i) transferring the data from the first data register to a second address register in response to the end-of-write signal;
- and
- (j) transferring the data from the second address register to a write driver in response to the write pulse signal, the write driver delivering the data to the memory array.
8 more elements
A method of accessing a memory array of a memory device, the method comprising the steps of:
- (a) generating a first write clock signal and a second write clock signal in response to a system clock signal and a write signal;
- (b) generating a write pulse signal in response to the first write clock signal;
- (c) generating an end-of-write signal in response to the first write clock signal and the write pulse signal;
- (d) storing an address in a first address register in response to the system clock signal;
- (e) transferring the address from the first address register to a second address register in response to the first write clock signal;
- (f) transferring the address from the second address register to a third address register in response to the end-of-write signal;
- (g) delivering the address from the third address register to the memory array in response to the write pulse signal;
- (h) storing data in a first data register in response to the second write clock signal;
- (i) transferring the data from the first data register to a second address register in response to the next second write clock signal;
- and
- (j) transferring the data from the second address register to a write driver in response to the write pulse signal, the write driver delivering the data to the memory array.
8 more elements
A method of accessing a memory array of a memory device, the method comprising the steps of:
- (a) generating a first write clock signal and a second write clock signal in response to a system clock signal and a write signal;
- (b) generating a write pulse signal in response to the first write clock signal;
- (c) generating an end-of-write signal in response to the first write clock signal and the write pulse signal;
- (d) storing an address in a first address register in response to the system clock signal;
- (e) transferring the address from the first address register to a second address register in response to the first write clock signal;
- (f) transferring the address from the second address register to a third address register in response to the next first write clock signal;
- (g) delivering the address from the third address register to the memory array in response to the write pulse signal;
- (h) storing data in a first data register in response to the second write clock signal;
- (i) transferring the data from the first data register to a second address register in response to the end-of-write signal;
- and
- (j) transferring the data from the second address register to a write driver in response to the write pulse signal, the write driver delivering the data to the memory array.
8 more elements
A memory device comprising:
- a write clock signal generator delivering a first write clock signal and a second write clock signal in response to a system clock signal and a write signal;
- a write pulse generator delivering a write pulse signal in response to the first write clock signal;
- an end-of-write signal generator delivering an end-of-write signal in response to the first write clock signal and the write pulse signal;
- a first address register for storing an address in response to the system clock signal;
- a second address register coupled to the first address register, the first address register transferring the address to the second address register in response to the first write clock signal;
- a third address register coupled to the second address register, the second address register transferring the address to the third address register in response to one of the end-of-write signal and the next first write clock signal;
- a memory array coupled to the third address register, the third address register transferring the address to the memory array in response to the write pulse signal;
- a first data register for storing data in response to the second write clock signal;
- a second data register coupled to the first data register, the first data register transferring the data to the second address register in response to one of the end-of-write signal and the next second write clock signal;
- and
- a write driver coupled to the second data register, the second address register transferring the data to the write driver in response to the write pulse signal, the write driver delivering the data to the memory array.
8 more elements
A processor-based device comprising:
- a processor;
- a memory device coupled to the processor, the memory device comprising:
- a write clock signal generator delivering a first write clock signal and a second write clock signal in response to a system clock signal and a write signal;
- a write pulse generator delivering a write pulse signal in response to the first write clock signal;
- an end-of-write signal generator delivering an end-of-write signal in response to the first write clock signal and the write pulse signal;
- a first address register for storing an address in response to the system clock signal;
- a second address register coupled to the first address register, the first address register transferring the address to the second address register in response to the first write clock signal;
- a third address register coupled to the second address register, the second address register transferring the address to the third address register in response to one of the end-of-write signal and the next first write clock signal;
- a memory array coupled to the third address register, the third address register transferring the address to the memory array in response to the write pulse signal;
- a first data register for storing data in response to the second write clock signal;
- a second data register coupled to the first data register, the first data register transferring the data to the second address register in response to one of the end-of-write signal and the next second write clock signal;
- and
- a write driver coupled to the second data register, the second address register transferring the data to the write driver in response to the write pulse signal, the write driver delivering the data to the memory array.
10 more elements
Dependencies are inferred from the claim text.