Semiconductor memory device and method of changing output data of the same
AssigneeFujitsu Limited
InventorMasamichi Mukai
Life of this patent
Estimating the term…
Abstract
The present invention provides a method for changing output data of a multiple-port semiconductor memory device, including memory cells, first and second bit lines connected to the memory cells, a first port connected to the first bit line to write data to the memory cells, a second port connected to the second bit line to output data stored in the memory cells, and a data read circuit connected to the second bit line and having a latch circuit for holding the data of one of the memory cells. The method of the present invention detects a change in the stored data in the memory cell associated with the data held by the latch circuit based on a potential at the second bit line, and changes the data held by the latch circuit when a change in the stored data is detected.
Claims16
A method for changing output data of a semiconductor memory device having a plurality of ports, wherein the semiconductor memory device includes a plurality of memory cells, a first bit line connected to the memory cells, a second bit line connected to the memory cells, a first port connected to the first bit line for writing input data to the memory cells via the first bit line, a second port connected to the second bit line for outputting data stored in the memory cells via the second bit line, and a data read circuit connected to the second bit line and including a latch circuit for holding the data of one of the memory cells, the method comprising the steps of:
- detecting a change in the stored data in the memory cell based on a potential at the second bit line;
- and
- changing the data held by the latch circuit when a change in the stored data is detected.
A semiconductor memory device comprising:
- a plurality of memory cells;
- a first word line connected to the memory cells;
- a second word line connected to the memory cells;
- a first bit line connected to the memory cells;
- a second bit line connected to the memory cells;
- a first port connected to the first word line and the first bit line for writing input data to the memory cells via the first bit line by activating the first word line;
- and
- a second port connected to the second word line and the second bit line for outputting data stored in each of the memory cells via the second bit line by activating the second word line, wherein the second port includes;
- a data read circuit connected to the second bit line for receiving the stored data and generating output data from the stored data;
- a data holding circuit connected to the data read circuit for holding the output data and generating holding data;
- a data change detection circuit connected to the second bit line for detecting whether the stored data has been changed based on a potential at the second bit line;
- and
- a data changing circuit connected to the data change detection circuit and the data holding circuit for changing the output data using the holding data.
A delay line comprising:
- a plurality of memory cells;
- a first word line connected to the memory cells;
- a second word line connected to the memory cells;
- a first bit line connected to the memory cells;
- a second bit line connected to the memory cells;
- a first port connected to the first word line and the first bit line for writing input data to the memory cells via the first bit line by activating the first word line;
- and
- a second port connected to the second word line and the second bit line for outputting data stored in each of the memory cells via the second bit line by activating the second word line, wherein the second port includes;
- a data read circuit connected to the second bit line for receiving the stored data and generating output data from the stored data;
- a data holding circuit connected to the data read circuit for holding the output data and generating holding data;
- a data change detection circuit connected to the second bit line for detecting whether the stored data has been changed based on a potential at the second bit line;
- and
- a data changing circuit connected to the data change detection circuit and the data holding circuit for changing the output data using the holding data.
A multiport memory comprising:
- a plurality of memory cells;
- a first word line connected to the memory cells;
- a second word line connected to the memory cells;
- a first bit line connected to the memory cells;
- a second bit line connected to the memory cells;
- a first port connected to the first word line and the first bit line for writing input data to the memory cells via the first bit line by activating the first word line;
- and
- a second port connected to the second word line and the second bit line for outputting data stored in each of the memory cells via the second bit line by activating the second word line, wherein the second port includes;
- a data read circuit connected to the second bit line for receiving the stored data and generating output data from the stored data;
- a data holding circuit connected to the data read circuit for holding the output data and generating holding data;
- a data change detection circuit connected to the second bit line for detecting whether the stored data has been changed based on a potential at the second bit line;
- and
- a data changing circuit connected to the data change detection circuit and the data holding circuit for changing the output data using the holding data.
Dependencies are inferred from the claim text.