Method and system for accessing rows in multiple memory banks within an integrated circuit

A method for accessing rows of memory cells in a plurality of respective memory banks in an integrated circuit, the integrated circuit including a row timing circuit that generates a row access command a delay time after being activated, comprising:

• decoding a first bank address and selecting one of the memory banks corresponding to the decoded first bank address;
• activating the row timing circuit a first time and storing the row access command generated by the row timing circuit;
• applying the stored row control signal to the selected one of the memory banks and accessing a row in that memory bank responsive to the applied row access command;
• decoding a second bank address and selecting a different one of the memory banks corresponding to the decoded second bank address;
• activating the row timing circuit and storing the row access command generated by the row timing circuit;
• and
• applying the stored row control signal to the selected different one of the memory banks and accessing a row in that memory bank responsive to the applied row access command.

A method for accessing rows of memory cells in a plurality of respective memory banks in an integrated circuit, the integrated circuit including a row timing circuit that generates a row access command a delay time after being activated, comprising:

• sequentially decoding bank addresses, each decoded bank address having a value corresponding to a respective one of the memory banks;
• sequentially activating the row timing circuit responsive to each decoded bank address to thereby sequentially generate row access commands;
• storing the sequentially generated row access commands;
• and
• applying each of the stored row access commands to a respective one of the memory banks determined by the corresponding decoded bank address, and accessing a row of memory cells in each such memory bank responsive to the applied row access command.

A method for accessing rows of memory cells in a plurality of respective memory banks in an integrated circuit, the integrated circuit including a plurality of row timing circuits that each generates a row access command a delay time after being activated, the number of row timing circuits being less than the number of memory banks, comprising:

• sequentially decoding bank addresses, each decoded bank address having a value corresponding to a respective one of the memory banks;
• sequentially selecting respective ones of the row timing circuits responsive to each decoded bank address, the selected row timing circuit being one of the row timing circuits not selected responsive to the previous decoded bank address;
• storing the row access commands generated by each sequentially selected row timing circuit;
• and
• applying each of the stored row access commands to a respective one of the memory banks, the respective one of the memory banks being the memory bank corresponding to the decoded bank address that caused the row access command to be generated;
• and
• accessing a row of memory cells in each memory bank responsive to the applied row access command.