Multi-bank semiconductor memory device suitable for integration with logic

A semiconductor integrated circuit device comprising:

• a plurality of banks arranged in a rectangular region and having data access made alternatively thereto;
• bank control circuitry provided in a prescribed region between regions where said plurality of banks are arranged, for controlling at least data access to said plurality of banks;
• and
• an internal access data transmission bus arranged in a region different from the prescribed region where said bank control circuitry is provided and coupled to each of the banks, for supplying and receiving data, wherein
• said plurality of banks include a plurality of memory arrays arranged on both sides of a first region extending in a first direction in said rectangular region,
• said bank control circuitry includes bank control circuits arranged between the memory arrays on each of both sides of said first region, and
• said internal access data transmission bus is arranged extending in said first direction in said first region.

A semiconductor integrated circuit device comprising:

• a plurality of banks arranged in a rectangular region and having data access made alternatively thereto;
• bank control circuitry provided in a prescribed reion between regions where said plurality of banks are arranged, for controlling at least data access to said plurality of banks;
• an internal access data transmission bus, extending in a first direction to reach two opposite sides of said rectangular region, arranged in a region different from the prescribed region where said bank control circuitry is provided and coupled to each of the banks, for supplying and receiving data, said two opposite sides extending in a second direction perpendicular to said first direction;
• a first logical processing circuit arranged on one side of said two opposite sides and connected to said internal access data transmission bus;
• and
• a second logical processing circuit arranged opposite to said first logical processing circuit on another side of said two opposite sides and connected to said internal access data transmission bus.

A semiconductor integrated circuit device comprising:

• a plurality of banks arranged in a rectangular region and having data access made alternatively thereto;
• bank control circuitry provided in a prescribed region between regions where said plurality of banks are arranged for controlling at least data access to said plurality of banks;
• an internal access data transmission bus extending in a first direction to reach two opposite sides of said rectangular region, arranged in a region different from the prescribed region where said bank control circuitry is provided and coupled to each of the banks, for supplying and receiving, data, said two opposite sides extending in a second direction perpendicular to said first direction;
• a logical processing circuit arranged on one side of said two opposite sides and connected to said internal access data transmission bus;
• and
• a testing circuit arranged on another side of said two opposite sides and connected to said internal access data transmission bus, for conducting a test for at least said plurality of banks.

A semiconductor integrated circuit device comprising:

• a plurality of banks arranged in a rectangular region and having data access made alternatively thereto;
• bank control circuitry provided in a prescribed region between regions where said plurality of banks are arranged for controlling at least data access to said plurality of banks;
• and
• an internal access data transmission bus arranged in a region different from the prescribed region where said bank control circuitry is provided and coupled to each of the banks, for supplying and receiving data, wherein
• said plurality of banks include a plurality of subbanks that are aligned with each other in a first direction on each of both sides of a first region extending in the first direction, each of said plurality of subbanks includes:
• a memory array having a plurality of memory cells arranged in rows and columns, column selection circuitry arranged on one side of said memory array in a direction of extension of the columns for selecting an addressed column, a write circuit arranged adjacent to said column selection circuitry for writing data into a selected memory cell of said memory array, and
• a read circuit arranged on another side opposite to said one side of said memory array, for reading data from said selected memory cell, and wherein
• said internal access data transmission bus includes a write data bus commonly coupled to write circuits of the subbanks arranged in alignment with each other in the first direction, and a read data bus commonly coupled to read circuits of the subbanks arranged in alignment with each other in the first direction.

A semiconductor integrated circuit device comprising:

• a plurality of banks arranged in a rectangular region and having data access made alternatively thereto;
• bank control circuitry provided in a prescribed region between regions where said plurality of banks are arranged, for controlling at least data access to said plurality of banks;
• and
• an internal access data transmission bus arranged in a region different from the prescribed region where said bank control circuitry is provided and coupled to each of the banks, for supplying and receiving data, wherein
• each of said plurality of banks includes a memory array having a plurality of memory cells arranged in rows and columns and a write/read circuit for writing and reading of data to and from said memory array, and
• said internal access data transmission bus is arranged extending over and above said memory array and coupled to said write/read circuit.

A semiconductor integrated circuit device comprising:

• a plurality of banks arranged in a rectangular region and having data access made alternatively thereto:
• bank control circuitry provided in a prescribed region between regions where said plurality of banks are arranged, for controlling at least data access to said plurality of banks;
• and
• an internal access data transmission bus arranged in a region different from the prescribed region where said bank control circuitry is provided and coupled to each of the banks, for supplying and receiving data,
• a logical processing circuit provided on an outside of said rectangular region and having an output for outputting a signal including data for access to said plurality of banks through said internal access data transmission bus, and
• a testing circuit provided adjacent to said logical processing circuit on the outside of said rectangular region and coupled to said internal access data transmission bus and outputting a signal for conducting at least a function test for said plurality of banks via an output thereof in accordance with a supplied signal.

A semiconductor integrated circuit device comprising:

• a plurality of banks arranged in a rectangular region and having data access made alternatively thereto:
• bank control circuitry provided in a prescribed region between regions where said plurality of banks are arranged for controlling at least data access to said plurality of banks;
• and
• an internal access data transmission bus arranged in a region different from the prescribed region where said bank control circuitry is provided, and coupled to each of the banks for supplying and receiving data, wherein
• said plurality of banks include four subbanks respectively arranged in four regions divided by a first region extending in a first direction and a second region extending in a second direction perpendicular to said first direction and crossing said first region;
• each of said plurality of subbanks includes:
• a memory array having a plurality of memory cells arranged in rows and columns;
• and
• an array circuit for performing an operation related to memory cell selection of said memory array under control by said bank control circuitry and, including components of the same circuit pattern repeatedly arranged in said second direction and arranged facing to said second region,
• said bank control circuitry is arranged in said first region,
• said second region includes an interconnection-dedicated region placed between array circuits of subbanks arranged opposite to each other with respect to said second region, and having at least an interconnection line for transmitting a signal and voltage for said bank control circuitry dedicatedly placed, and
• a circuit portion performing a prescribed processing in response to a supplied signal is formed in a region other than said interconnection-dedicated region.

A semiconductor device comprising:

• a plurality of banks each including:
• a memory array having a plurality of memory cells arranged in rows and columns,
• a plurality of sense amplifiers arranged corresponding to said columns respectively, each for sensing and amplifying a signal on a corresponding column,
• a sense amplifier power supply line arranged over said memory array, for transmitting an operation power supply voltage to said plurality of sense amplifiers,
• a plurality of main power supply lines arranged on both opposing sides opposite to each other of said memory array respectively and each coupled to receive a power supply voltage, for transmitting said power supply voltage to supply the power supply voltage at least to a peripheral circuit for making data access to a corresponding bank, and
• a plurality of sub power supply lines arranged in a layer higher than said sense amplifier power supply line over said memory array and coupled to said plurality of main power supply lines.

A semiconductor integrated circuit device comprising:

• a plurality of memory arrays arranged facing a first region placed extending in a first direction and a second region placed extending in a second direction perpendicular to said first direction, each of the memory arrays including a plurality of memoir cells arranged in rows and columns;
• an array circuit arranged corresponding to each of said memory arrays and arranged facing said first region, performing an operation related to memory cell selection of a corresponding memory array, and having components of a same pattern repeatedly arranged in said first direction;
• a peripheral circuitry region placed in said second region for arranging peripheral circuitry including at least a control circuit for controlling an operation of said array circuit;
• and
• an interconnection-dedicated region arranged in said first region between array circuits of memory arrays placed opposite to each other with respect to said first region, and having at least an interconnection line for transmitting a signal and voltage for said control circuit arranged exclusively.