Integrated memory having memory cells and reference cells
AssigneeInfineon Technologies AG
InventorPeter Pöchmüller
Life of this patent
Estimating the term…
Abstract
Memory cells are arranged at crossover points of word lines WLi and bit lines. First reference cells are arranged at crossover points of at least one first reference word line and bit lines. In a normal operating mode, the reference cells serve for generating a reference potential on the bit lines prior to a readout of the memory cells. Second reference cells are arranged at crossover points of at least one second reference word line and the bit lines. In a test operating mode, the second reference cells serve for generating a reference potential on the bit lines prior to a readout of the reference cells.
Claims4
An integrated memory, comprising:
- word lines and bit lines and a plurality of memory cells arranged at respective crossover points of said word lines and said bit lines;
- first reference cells arranged at crossover points of at least one first reference word line and said bit lines, said first reference cells, in a normal operating mode, generating a reference potential on said bit lines prior to a readout of said memory cells;
- second reference cells arranged at crossover points of at least one second reference word line and said bit lines, said second reference cells, in a test operating mode, generating a reference potential on said bit lines prior to a readout of said first reference cells.
Dependencies are inferred from the claim text.