Semiconductor memory device having structure for high-speed data processing
AssigneesMitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Company Limited
InventorHiroaki Tanizaki
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Abstract
The semiconductor memory device separates data input/output lines into a pair of write data lines and a pair of read data lines. A write gate is turned on with a column selection signal for writing, and a read gate is turned on with a column selection signal for reading. The pair of write data lines are not precharged but only the pair of read data lines are precharged in a transition to each operation. The pair of write data lines are precharged with a write mask signal in write masking. Thus, high-speed data processing is implemented.
Claims20
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells arranged in rows and columns, a plurality of word lines and a plurality of pairs of bit lines;
- a selection circuit selecting a memory cell subjected to a write operation/read operation from said plurality of memory cells;
- a pair of write data lines for transferring write data to said memory cell array;
- a pair of read data lines for transferring data read from said memory cell array;
- and
- a write driver driving said pair of write data lines in response to said write data and precharging said pair of write data lines in response to a write mask signal in said write operation.
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells arranged in rows and columns, a plurality of word lines and a plurality of pairs of bit lines;
- columns, a plurality of word lines and a memory cell from said plurality of memory cells;
- a pair of data lines for transferring data to/from said memory cell array;
- a write driver driving said pair of data lines in response to said data and precharging said pair of data lines in response to a write mask signal.
Dependencies are inferred from the claim text.