Semiconductor integrated circuit device including tester circuit for defective memory cell replacement
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTsukasa Ooishi, Hideto Hidaka
Life of this patent
Estimating the term…
Abstract
Following data writing into a memory cell array according to an internal address signal, the data read out from each memory cell is compared with expected value data in a readout operation. A row decoder selects a plurality of memory cells belonging to the same row in the memory cell array at one time according to an address signal. A BIST circuit determines that repair is to be carried out with a spare memory cell row, not a spare memory cell column, when a plurality of defective memory cells are detected from the plurality of memory cells selected at one time.
Claims10
A semiconductor integrated circuit device comprising:
- a memory cell array having a plurality of memory cells arranged in a matrix, each memory cell storing data,
- said memory cell array including
- a normal memory cell array with a plurality of normal memory cells,
- a spare memory cell row with a plurality of spare memory cell rows, and
- a spare memory cell column with a plurality of spare memory cell columns;
- a memory cell select circuit to select a plurality of memory cells belonging to the same row in said memory cell array at one time according to an address signal;
- a data transmission circuit to transfer said stored data with respect to said selected plurality of memory cells;
- and
- tester circuit detecting a defective memory cell in said memory cells, and determining which of said spare memory cell is to be used for replacement,
- said tester circuit including
- a comparison circuit comparing stored data from said selected memory cell with expected value data in a test readout operation,
- an address storage circuit to store a defective address corresponding to a defective memory cell according to a comparison result of said comparison circuit, and
- a control circuit to control a test operation, said control circuit determining repair using said spare memory cell row when a plurality of defective memory cells are detected from said plurality of memory cells selected at one time.
Dependencies are inferred from the claim text.