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US 6,310,806 B1Granted
Semiconductor memory device with redundant circuit
AssigneeKabushiki Kaisha Toshiba
InventorsTomoki Higashi, Hiroaki Nakano
Life of this patent
Estimating the term…
Abstract
A redundant memory circuit stores a defective row address. A switch circuit connects a spare row decoder with the wire for transmitting a row address signal according to the defective row address stored in the redundant memory circuit when the power supply is turned on. A row decoder deactivating circuit, when the power supply is turned on, deactivates the part of the row decoder corresponding to the defective row address according to the defective row address stored in the redundant memory circuit. As a result, when the row address buffer outputs the row address signal corresponding to the defective row address, the spare row decoder decodes the row address signal, thereby selecting a spare word line immediately.
Claims20
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells arranged in rows and columns;
- a spare cell array including spare cells, said spare cells being to be replaced with defective memory cells in said memory cell array;
- a memory circuit for storing the addresses of said defective memory cells;
- an address buffer for outputting addresses for selecting said memory cells;
- a decoder for selecting a memory cell in said memory cell array according to the address signal outputted from said address buffer and which includes a select circuit for said memory cells and a control circuit for deactivating said select circuit according to the address signal for said defective memory cell;
- a spare decoder for selecting a spare cell in said spare array;
- and
- a switch circuit which is connected between said spare decoder and said address buffer and which enables only the defective address supplied from said address buffer to pass through according to the address of the defective memory cell outputted from said memory circuit when a power supply is turned on.
5 more elements
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells arranged in rows and columns;
- a spare cell array which is arranged adjacent to said memory cell array and includes spare cells;
- an address buffer for outputting addresses for selecting said memory cells;
- a memory circuit for storing the address of a defective memory cell in said memory cell array;
- a switching circuit which is connected between said memory circuit and address buffer and which outputs the defective address outputted from said memory circuit at the time of turning on a power supply and, in a normal operation, outputs the address from said address buffer;
- a decoder for selecting a memory cell in said memory cell array according to the address signal outputted from said switching circuit;
- a spare decoder for selecting a spare cell in said spare cell array;
- and
- a switch circuit which is connected between the output terminal of said switching circuit and spare decoder and which does switching in such a manner that it enables only the address of the defective memory cell supplied from said address buffer to pass through according to the address of the defective memory cell outputted from said switching circuit at the time of turning on the power supply, wherein
- said decoder includes a select circuit for selecting the memory cell corresponding to said defective address according to the defective address supplied from said switching circuit and a control circuit for deactivating the select circuit.
7 more elements
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cell blocks, each of said memory cell blocks having a plurality of memory cells arranged in rows and columns;
- spare cell arrays arranged adjacent to said respective memory cell blocks, each of said spare cell arrays including a plurality of spare cells, said spare cell being to be replaced with defective memory cells in said memory cell array;
- an address buffer for outputting an address for selecting a memory cell in each of said memory cell blocks;
- a plurality of decoders for selecting a memory cell in each of said memory cell blocks according to the address outputted from said address buffer and which each includes a select circuit for said memory cell and a control circuit for deactivating said select circuit according to the address signal for said defective memory cell;
- a plurality of spare decoders for selecting spare cells in said respective spare cell arrays;
- a plurality of driving circuits for driving a spare cell according to the output signal of each of said spare decoders;
- a plurality of memory circuits for storing the address of a defective memory cell in each of said memory cell blocks;
- and
- a plurality of switch circuits which are connected between said address buffer and said respective spare decoders and which do switching in such a manner that they enable only the address of the defective memory cell supplied from said address buffer to pass through according to the address of the defective memory cell outputted from said memory circuit at the time of turning on a power supply.
6 more elements
Dependencies are inferred from the claim text.