Architecture for a dual-bank page mode memory with redundancy
AssigneesAdvanced Micro Devices, Inc., Fujitsu Limited
InventorsYasushi Kasa, Ming-Huei Shing
Life of this patent
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Abstract
A memory circuit (100) includes address circuitry (104) configured to receive address data and a plurality of I/O buffers (112). A core cell array (102) includes core cells and redundant core cells. Sense amplifiers (108) including read sense amplifiers (132) and redundant sense amplifiers may be coupled to the I/O buffers by word selection circuitry (110). Redundancy is implemented on an I/O-by-I/O basis, so that a redundant core cell and sense amplifier may be substituted for any failed bit in the core cell array.
Claims11
A memory circuit comprising:
- address circuitry configured to receive address data;
- output circuitry configured to provide a predetermined number of bits of stored data from the memory circuit;
- a core cell array including a plurality of core cells and a plurality of redundant core cells;
- sense amplifiers, including
- read sense amplifiers coupled to the core cells, and
- redundant sense amplifiers coupled to the redundant core cells;
- and
- word selecting circuitry coupled to the sense amplifiers and operative in response to the address data to couple a subset of the read sense amplifiers to the output circuitry, the word selecting circuitry inhibiting a failed read sense amplifier and coupling a redundant sense amplifier in place of the failed read sense amplifier.
A memory circuit comprising:
- address circuitry configured to receive address data corresponding to an addressed word of data to be accessed from the memory circuit;
- a plurality of I/O buffers configured to communicate data externally to the memory circuit;
- a core cell array including core cells and redundant core cells;
- sense amplifiers, including
- read sense amplifiers associated with the core cells and configured to sense page data including the addressed word of data and a predetermined number of words of data;
- and
- redundant sense amplifiers associated with the redundant core cells;
- and
- word selection circuitry configured to couple sense amplifiers associated with the addressed word of data to the plurality of I/O buffers in response to the address data, the word selection circuitry further configured to couple a redundant sense amplifier to an I/O buffer in place of a failing bit of the core cell array and to inhibit a failed read sense amplifier associated with the failing bit.
A method for operating a memory circuit including a core cell array, the method comprising the steps of:
- receiving address data corresponding to a word of data to be read from the core cell array;
- reading page mode data including the word of data and a plurality of related words from the core cell array;
- when the page mode data includes one or more failed bits, replacing only the one or more failed bits with redundant data;
- and
- in response to the address data, providing output data selected from the page mode data and the redundant data.
Dependencies are inferred from the claim text.