Device and method for repairing a semiconductor memory

A redundancy architecture in a semiconductor memory having a first sub-array and second sub-array, the redundancy architecture including circuitry for storing row addresses of defective rows in the first sub-array and second sub-array and for activating a redundant row in one sub-array of the first sub-array and second sub-array in response to receiving a row address matching one of the stored defective row addresses while disabling a redundant row arranged in the other sub-array of the first sub-array and second sub-array in an order complementary to that of the activated redundant row, the circuitry comprising:

• a plurality of fuse banks storing the defective row addresses and outputting a match signal in response to receiving a row address matching the one of the stored defective row addresses;
• at least one first row decoder and at least one second row decoder connected to the respective first sub-array and second sub-array activating the redundant rows in the first sub-array and second sub-array in response to receiving the match signal;
• and
• a plurality o of enable fuses connected between the plurality of fuse banks and the at least one first row decoder and at least one second row decoder conducting the match signal to the row decoder coupled to the one sub-array of the first sub-array and second sub-array and isolating the match signal from the row decoder coupled to the other sub-array of the first sub-array and second sub-arrays disabling activation of the redundant row in the other sub-array of the first sub-array and second sub-array.

A method of providing redundant memory storage for a semiconductor memory having a plurality of memory cells arranged rows of memory cells forming sub-arrays of memory cells, said sub-arrays of memory cells forming at least one array of memory cells in the semiconductor memory, comprising:

• identifying the row addresses of defective memory cells in rows of memory cells of said semiconductor memory;
• storing row addresses of defective rows in a pair of sub-arrays in the semiconductor memory;
• activating a redundant row in one sub-array of the pair of sub-arrays in response to receiving a row address matching one of the stored defective row addresses;
• and
• disabling activation of a redundant row arranged in the other sub-array of the pair of sub-arrays in an order complementary to that of the activated redundant row when a match signal is isolated from a row decoder associated with the other sub-array of the pair of sub-arrays.