Method and device for fast addressing redundant columns in a nonvolatile memory

A method for addressing redundant columns in a nonvolatile memory receiving at inputs selection addresses, each redundant column including a respective bit line, the method comprising:

• detecting a transition in said selection addresses;
• starting charging of all said bit lines upon detection of said transition in the addresses;
• detecting, after starting charging of all said bit lines, whether one of said redundant columns is addressed;
• if one of said redundant columns is addressed, continuing charging of the bit line of the redundant column addressed and interrupting charging of the bit lines of the redundant columns not addressed;
• and
• if none of said redundant columns is addressed, interrupting charging of all said bit lines.

A device for addressing a redundant column in a nonvolatile memory receiving at inputs selection addresses, the redundant column including a bit line, the device comprising:

• charging means connected to said bit line and selectively activatable for charging the bit line;
• first detecting means for detecting a transition in said selection addresses;
• second detecting means for detecting whether said redundant column is addressed;
• and
• control means connected to said first and second detecting means and to said charging means for controlling start of charging of said bit line upon detection of said transition in said selection addresses, and subsequently controlling interruption of charging of said bit line should said redundant column not be addressed.

A device for addressing a plurality of redundant columns in a nonvolatile memory receiving at inputs selection addresses, each redundant column including a respective bit line, the device comprising:

• charging means connected to said bit lines and selectively activatable for charging the bit lines independently from one another;
• first detecting means for detecting a transition in said selection addresses;
• second detecting means for detecting whether one of said redundant columns is addressed;
• and
• control means connected to said first and second detecting means and to said charging means for controlling start of charging of all said bit lines upon detection of said transition in the addresses and subsequently controlling interruption of charging of the bit lines of the non-addressed redundant columns.

A device for addressing a redundant column of a memory, the redundant column including a bit line, the device comprising:

• an address transition detector for detecting a transition in an address directed to the memory, the address transition detector having an output that provides a transition detection signal that indicates the transition;
• a charging switch connected between a charging voltage and the bit line and including a control terminal;
• an address detector for detecting whether the redundant column is addressed by the address, the address detector having an output that indicates whether the redundant column is being addressed;
• and
• a control stage having a first input and a second input coupled to the outputs of the address transition detector and the address detector, respectively, and an output coupled to the control terminal of the charging switch, the control stage being structured to cause the charging switch to start charging the bit line upon detection of the address transition, and subsequently interrupt the charging of the bit line in response to receiving from the address detector an indication that the redundant column is not being addressed.