US 6,310,798 B1 · Semiconductor memory and method for manufacture thereof

Abstract

A semiconductor memory which can secure the stability of data holding characteristics and data read/write characteristics for a tunnel diode having a small peak/valley ratio, and to provide a method for manufacturing such a semiconductor memory. The peak/valley ratio of a tunnel diode can be improved by arranging a tunnel insulating film on the bottom portion of the ground direct contact forming the tunnel diode; the resistance of high resistance load can further be increased by arranging a tunnel insulating film on the bottom portion of the storage node direct contact; and data holding characteristics can be improved while controlling the column current by setting the power voltage impressed to the high resistance load higher than the power voltage impressed to the bit line. Stable data read/write characteristics can be secured while controlling the column current by increasing drain resistance by utilizing the drain region side of the access transistor as a P−-type active region, and by arranging a tunnel insulating film on the bottom portion of the bit-line direct contact.

Claims20

Dependent claims

A semiconductor memory selected by a bit line and a word line comprising:

an access transistor whose source-drain region side is connected to said bit line and whose gate side is connected to said word line;
a loading resistor connected between a power source and a storage node on the drain region side of said access transistor;
and
a negative resistor portion connected between ground and the storage node on the drain region side of said access transistor,
wherein:
said negative resistor portion has a tunnel insulating film which produces the tunnel effect and is formed on the p-type active region, and has n-type polysilicon formed in said tunnel insulating film, and
the drain region of said access transistor includes a P-type region forming. a negative resistor portion.

4 more elements

A semiconductor memory comprising

a semiconductor substrate of the first conductivity type;
a well of the second conductivity type formed on the main surface of said semiconductor substrate of the first conductivity type;
a first active region of the first conductivity type formed on said well of the second conductivity type, and having a relatively high impurity concentration;
an access transistor whose source region side is connected to the storage node formed in said first active region;
a second active region of the first conductivity type formed on said well of the second conductivity type other than the area of said first active region and said access transistor, and having a relatively high impurity concentration;
a storage node direct contact formed on the upper portion of said storage node;
a loading resistor connected between said storage node and the power line;
a bit-line direct contact formed on the upper portion of said second active region;
a bit line formed through said bit-line direct contact;
a ground direct contact formed on the upper portion of said first active region;
a polysilicon ground wiring formed by forming a polysilicon film on said ground direct contact;
a ground contact placed on said polysilicon ground wiring;
and
a ground line formed on said ground contact,
wherein a tunnel insulating film producing the tunneling effect is provided on the bottom portion of said ground direct contact.

12 more elements

Dependencies are inferred from the claim text.

Semiconductor memory and method for manufacture thereof

Life of this patent

Semiconductor memory and method for manufacture thereof

Life of this patent

Abstract

Claims20