Drive method for FeRAM memory cell and drive device for the memory cell

Abstract

A method is disclosed for driving a memory cell formed of a ferroelectric capacitor FC and a transistor Tr. While maintaining a cell plate line CP at an intermediate voltage level Vcc/2 of a power supply voltage, a bit line BL is precharged to a voltage equal to Vcc/2. Data is read by detecting a change in voltage on the bit line BL which occurs when the bit line BL is released from the precharged state in a period in which word line WL0 is selected. Data is written by changing the voltage on the cell plate line CP in a stepped fashion in the order of Vcc/2, Vcc, 0 V, and Vcc/2, while applying a write voltage to the bit line after releasing the bit line from the precharged state, in a period in which a word line is selected. This method allows a ferroelectric memory cell to be driven at a high speed with low power consumption. Furthermore, the method allows a ferroelectric memory cell to be polarized to a sufficient degree, and thus the ferroelectric memory cell can be driven in a highly reliable fashion.

Dependencies are inferred from the claim text.