Semiconductor memory device with data retention characteristic of improved stability

A semiconductor memory device formed on a main surface of a semiconductor substrate, comprising:

• a memory array including a plurality of memory cells arranged in a matrix of rows and columns;
• a plurality of word lines respectively provided to rows of said plurality of memory cells;
• and
• a plurality of bit line pairs respectively provided to columns of said plurality of memory cells and each including first and second bit lines, wherein
• each of said plurality of memory cells includes
• first and second access transistors, having their respective gates connected to a same one of said plurality of word lines, for connecting said first and second bit lines to first and second internal nodes, respectively,
• a first driver transistor connected between a power-supply node to which an inactivating potential is provided and said first internal node and having a gate connected to said second internal node, and
• a second driver transistor connected between said power-supply node to which the inactivating potential is provided and said second internal node and having a gate connected to said first internal node, said semiconductor memory device further comprising:
• a row select circuit for selecting one of said plurality of word lines according to a row address signal and for providing an activating potential to a selected word line and providing an inactivating potential to unselected word lines when making an access to said memory array, and for providing to said plurality of word lines an intermediate potential between said activating potential and said inactivating potential when the access to said memory array is completed;
• and
• a precharging circuit for precharging said plurality of bit lines after the access to said memory array is completed.