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US 6,310,669 B1Granted
TFT substrate having connecting line connect to bus lines through different contact holes
AssigneesMitsubishi Denki Kabushiki Kaisha, Advanced Display Inc.
InventorsKazuhiro Kobayashi, Nobuhiro Nakamura, Yukio Endoh
Life of this patent
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Abstract
A TFT array substrate including: an insulating substrate, a gate electrode, a gate electrode line, an insulating film, a semiconductor layer, a contact layer, a source electrode, a drain electrode, a source electrode line, an interlayer insulating film, a pixel electrode, and a connecting line which is made of a same material that of the pixel electrode and connects electrically between the gate electrode line and the source electrode line through a second contact hole provided in the insulating film and a third contact hole provided in the interlayer insulating film.
Claims13
A TFT array substrate comprising:
- an insulating substrate,
- a gate electrode formed on said insulating substrate,
- a gate electrode line formed on said insulating substrate,
- an insulating film formed on said gate electrode, said gate electrode line and said insulating substrate except for whole of outer surface of said gate electrode and whole of outer surface of said gate electrode line,
- a semiconductor layer formed on said insulating film,
- a contact layer formed on said semiconductor layer,
- a source electrode connected to said contact layer,
- a drain electrode which is connected to said contact layer, said contact layer being divided into two portions, one of said two portions corresponding to said source electrode and the other one of said two portions corresponding to said drain electrode,
- a source electrode line connected to said source electrode,
- an interlayer insulating film formed on said gate electrode, said gate electrode line, said source electrode, said source electrode line and said drain electrode,
- a pixel electrode which is formed on said interlayer insulating film and is made of transparent conductive film and is connected electrically to said drain electrode through a first contact hole provided in said interlayer insulating film, and
- a connecting line which is made of a same material that of said pixel electrode and connects electrically between said gate electrode line and said source electrode line through a second contact hole provided in said insulating film and a third contact hole provided in said interlayer insulating film.
9 more elements
A method of manufacturing a TFT array substrate comprising
- an insulating substrate,
- a gate electrode formed on said insulating substrate,
- a gate electrode line formed on said insulating substrate,
- an insulating film formed on said gate electrode, said gate electrode line and said insulating substrate except for whole of outer surface of said gate electrode and whole of outer surface of said gate electrode line,
- a semiconductor layer formed on said insulating film,
- a contact layer formed on said semiconductor layer,
- a source electrode connected to said contact layer,
- a drain electrode which is connected to said contact layer, said contact layer being divided into two portions, one of said two portions corresponding to said source electrode and the other one of said two portions corresponding to said drain electrode,
- a source electrode line connected to said source electrode,
- an interlayer insulating film formed on said gate electrode, said gate electrode line, said source electrode, said source electrode line and said drain electrode,
- a pixel electrode which is formed on said interlayer insulating film and is made of transparent conductive film and is connected electrically to said drain electrode through a first contact hole provided in said interlayer insulating film, and
- a connecting line which is made of a same material that of said pixel electrode and connects electrically between said gate electrode line and said source electrode line through a second contact hole provided in said insulating film and a third contact hole provided in said semiconductor layer on said source electrode, said insulating film and said interlayer insulating film,
- said method comprising steps of:
- (a) forming said gate electrode and said gate electrode line on said insulating substrate,
- (b) depositing said insulating film on said gate electrode, said gate electrode line and said insulating substrate except for whole of outer surface of said gate electrode and whole of outer surface of said gate electrode line,
- (c) forming said semiconductor layer over said gate electrode through said insulating film and forming said contact layer on said semiconductor layer,
- (d) forming said source electrode and said drain
- electrode on said contact layer, and forming said source electrode line and etching said contact layer by using said source electrode and said drain electrode as masks,
- (e) depositing said interlayer insulating film on said source electrode, said source electrode line and said drain electrode,
- (f) providing simultaneously two of said first contact hole in said insulating film on said gate electrode and in said interlayer insulating film, said second contact hole in said interlayer insulating film on said source electrode line, and said third contact hole in said interlayer insulating film on said drain electrode, and
- (g) forming simultaneously said pixel electrode and said connecting line.
18 more elements
Dependencies are inferred from the claim text.