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US 6,310,596 B1Granted
Serial access memory
AssigneeOki Electric Industry Co., Ltd.
InventorAtsushi Takasugi
Life of this patent
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Abstract
A serial access memory having a first memory cell array and a second memory cell array. The serial access memory is provided with a control circuit for controlling the Most Significant Bit (MSB) of an address supplied to each of the first and second memory cell arrays. The control circuit causes the operations of circuits in the first memory cell array to become identical to those of circuits in the second memory cell array, thereby making it possible to read data at a high speed. An STN type LCD including the serial access memory, has a display device that facilitates production of memory maps in the memory cells without a need for externally-mounted elements such as a multiplexer.
Claims19
A serial access memory, comprising:
- a first memory cell array including a plurality of memory cells each storing data therein, and a plurality of first word lines for applying respective first selection signals to the respective memory cells;
- a second memory cell array including a plurality of memory cells each storing data therein, and a plurality of second word lines for applying respective second selection signals to the respective memory cells;
- a first data register, coupled to the first memory cell array, for latching the data transferred from the first memory cell array;
- a second data register, coupled to the second memory cell array, for latching the data transferred from the second memory cell array;
- a first address decoder, connected to the first memory cell array, for outputting the first selection signals selectively to the first word lines, so as to select any of the first word lines in response to first address data applied to said first address decoder;
- a second address decoder, connected to the second memory cell array, for outputting the second selection signals selectively to the second word lines, so as to select any of the second word lines in response to second address data applied to said second address decoder;
- and
- a control circuit, receiving address data that includes a most significant bit, the address data having a first portion which specifies addresses less than a predetermined address value and a second portion which specifies addresses equal to or greater than the predetermined address value, for converting the most significant bit of the address data to a predetermined bit value, applying the first portion of the address data, including the predetermined bit value, to the first address decoder as the first address data at a time that the data is transferred from the first and second memory cell arrays respectively to the first and second registers, and simultaneously applying the second portion of the address data, including the predetermined bit value, to the second address decoder as the second address data.
5 more elements
A serial access memory, comprising:
- a set of memory cells, the set of memory cells having a first memory cell group and a second memory cell group, each including a plurality of memory cells formed in rows and columns, each memory cell storing respective data;
- data register means for latching stored data transferred from the set of memory cells during a transferring period;
- a control circuit, receiving address data that includes a most significant bit, the address data having a first portion which specifies addresses less than a predetermined address value and a second portion which specifies addresses equal to or greater than the predetermined address value, for converting the most significant bit during the transferring period, so that the first portion of the address data is equal to the second portion of the address data;
- and
- address decoder means, to which the first and second portions of the address data are applied by said control circuit, for selecting memory cells in the first memory cell group in response to the first portion of the address data and for selecting memory cells in the second memory cell group in response to the second portion of the address data.
2 more elements
A serial access memory, comprising:
- a first memory cell array, including a plurality of memory cells storing data therein;
- a second memory cell array, including a plurality of memory cells storing data therein;
- a first data register coupled to the first memory cell array, for latching stored data transferred from the first memory cell array;
- a second data register, coupled to the second memory cell array, for latching stored data transferred from the second memory cell array;
- a first address decoder, connected to the first memory cell array, for selecting memory cells from among the memory cells of the first memory cell array, in response to first address data applied thereto;
- a second address decoder, connected to the second memory cell array, for selecting memory cells from among the memory cells of the second memory cell array, in response to second address data applied thereto;
- and
- a control circuit, receiving address data that includes a most significant bit, the address data having a first portion which corresponds to the first address data and which specifies addresses less than a predetermined address value and a second portion which corresponds to the second address data and which specifies addresses equal to or greater than the predetermined address value, for converting the most significant bit, at a time that the stored data is transferred from the first and second memory cell arrays to the first and second data registers, respectively, so that the first address data is equal to the second address data, and for applying the first address data and the second address data to the first and second address decoders, respectively.
5 more elements
A serial access memory, comprising:
- a set of memory cells, the set of memory cells having a first memory cell group and a second memory cell group, each group including a plurality of memory cells formed in rows and columns, each memory cell storing respective data;
- data register means for latching data transferred from the set of memory cells during a transferring period;
- control circuit means for receiving input address data having a most significant bit, for controlling the most significant bit to convert the input address data to first address data and second address data, the first address data being equal to the second address data, and for outputting the first and second address data during the transferring period;
- and
- address decoder means, receiving the first and second address data from the control circuit, for selecting memory cells in the first memory cell group in response to the first address data, and for selecting memory cells in the second memory cell group in response to the second address data.
2 more elements
A serial access memory, comprising:
- a first memory cell array which includes a plurality of word lines and memory cells connected to the word lines;
- a second memory cell array which includes a plurality of word lines and memory cells connected to the word lines;
- a bus having a plurality of pairs of lines, each pair of lines corresponding to a bit of an address signal which has a most significant bit, the pairs of lines including an MSB pair which corresponds to the most significant bit;
- means for applying the bits in inverted and non-inverted form to the corresponding pairs of lines;
- a first address decoder connected between the bus and the word lines of the first memory cell array;
- a second address decoder connected between the bus and the word lines of the second memory cell array;
- and
- MSB control means for bringing both of the MSB pair of lines a common digital state simultaneously during a data-reading operation.
5 more elements
Dependencies are inferred from the claim text.