Semiconductor integrated circuit having plural input control circuits

Abstract

A series to parallel A/D type converter converts an analog input signal to a digital output signal. The A/D converter has an upper rank comparator which performs A/D conversion of upper order bits and a lower rank comparator which performs A/D conversion of lower order bits. An input control circuit receives the analog input signal and generates a first input signal which is provided to the upper rank comparator and generates a second input signal which is provided to the lower rank comparator. Both the upper and lower rank comparators receive the respective first and second input signal from the input control circuit and compare the respective input signals with predetermined reference voltages to generate a digital output signal. The input control circuit includes first and second switches which each have a first terminal connected to a common node for receiving the analog input signal and a second terminal connected to the respective upper and lower rank comparators to provide the first and second input signals to the comparators. A third switch, which functions as an interchannel control circuit, connects the second terminals of the first and second switches.

Dependencies are inferred from the claim text.