Reference-free clock generation and data recovery PLL
AssigneeCypress Semiconductor Corporation
InventorKamal Dalmia
Life of this patent
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Abstract
An apparatus comprising a first circuit, a second circuit, and a logic circuit. The first circuit may be configured to generate one or more first control signals having a first data rate in response to an input signal having a second data rate and a clock signal having the first data rate. The second circuit may be configured to generate one or more second control signals in response to the input signal and the clock signal. The first logic circuit may be configured to generate the clock signal in response to the one or more first control signals, the one or more second control signals and a third control signal.
Claims19
An apparatus comprising:
- a first circuit configured to generate one or more first control signals having a first data rate in response to (i) an input signal having a second data rate and (ii) a clock signal having said first data rate;
- a second circuit configured to generate one or more second control signals having said first data rate in response to (i) said input signal and (ii) said clock signal;
- and
- a first logic circuit configured to generate said clock signal in response to (i) said one or more first control signals, (ii) said one or more second control signals and (iii) a third control signal, wherein one of said first control signals and said second control signals comprises a pump-up signal and another one of said first control signals and said second control signals comprises a pump-down signal.
An apparatus comprising:
- means for generating one or more first control signals having a first data rate in response to (i) an input signal having a second data rate and (ii) a clock signal having said first data rate;
- means for generating one or more second control signals having said first data rate in response to (i) said input signal and (ii) said clock signal;
- and
- means for generating said clock signal in response to (i) said one or more first control signals, (ii) said one or more second control signals and (iii) a third control signal, wherein one of said first control signals and said second control signals comprises a pump-up signal and another one of said first control signals and said second control signals comprises a pump-down signal.
A method for reference-free clock generation and data recovery, comprising the steps of:
- (A) generating one or more first control signals having a first data rate in response to (i) an input signal having a second data rate and (ii) a clock signal having said first data rate;
- (B) generating one or more second control signals having said first data rate in response to (i) said input signal and (ii) said clock signal;
- and
- (C) generating said clock signal in response to (i) said one or more first control signals, (ii) said one or more second control signals and (iii) a third control signal, wherein one of said first control signals and said second control signals comprises a pump-up signal and another one of said first control signals and said second control signals comprises a pump-down signal.
Dependencies are inferred from the claim text.