Generator scheme and circuit for overcoming resistive voltage drop on power supply circuits on chips

Apparatus for controlling voltage generators of a generator system on a chip comprising:

• at least one generator for generating a predetermined amount of power to load circuits on the chip;
• a power bus directed along a “spine” section on the chip which intersects with an “arm” section on the chip for supplying power from the at least one generator to circuits in adjacent sections of the chip, the bus comprising a feedback lead from each remote end of the “arm” section to at least the intersection of the “spine” and “arm” sections for providing a continuous measurement of a voltage drop occurring at each remote end of the “arm” section;
• and
• at least one detector circuit located adjacent the intersection of the “spine” and “arm” sections of the chip for comparing a voltage from the at least one generator measured at the intersection of the “spine” and “arm” sections with the voltage drop measured at each end of the “arm” section for providing control signals to the at least one generator for altering a generated voltage to maintain a predetermined power level on the power bus in response to load changes caused by the circuits in the adjacent sections of the chip.

Apparatus for controlling voltage generators of a generator system on a chip comprising:

• a plurality of generators for generating a predetermined amount of power to load circuits on the chip;
• a power bus directed along a “spine” section on the chip which intersects with an “arm” section on the chip for supplying power from the plurality of generators which are coupled via the power bus in the “spine” section thereof to circuits in adjacent sections of the chip, the bus comprising a feedback lead from the first and second remote ends of the power bus in the “arm” section to at least the intersection of the “spine” and “arm” sections for providing continuous measurements of a voltage drop occurring at the first and second remote ends of the “arm” section;
• and
• a first and a second detector circuit located adjacent the intersection of the “spine” and “arm” section of the chip on opposite sides of the intersection for comparing a voltage from the plurality of generators measured at the intersection of the “spine” and “arm” sections with the concurrent voltage drops measured at the first and second remote ends, respectively, of separate sections of the “arm” section for providing separate BOOST and SPEED control signals which are logically OR-combined and transmitted to the plurality of generators for altering an overall generated voltage to maintain a predetermined power level on the power bus in the “spine” and “arm” sections in response to load changes caused by the circuits in the adjacent sections of the chip.

A method for controlling voltage generators of a generator system on a chip comprising the steps of:

• (a) generating a predetermined amount of power from at least one generator for transmission along a power bus comprising a “spine” section on the chip which intersects with an “arm” section on the chip to load circuits in areas adjacent the “spine” and “arm” sections;
• (b) obtaining a continuous measurement of a voltage drop occurring at a remote end of the “arm” section via a feedback lead to at least the intersection of the “spine” and “arm” sections for providing a continuous measurement of a voltage drop occurring at each end of the “arm” section;
• (c) comparing a voltage from the at least one generator measured at the intersection of the “spine” and “arm” sections with the concurrent voltage drop measured at each end of the “arm” section in at least one detector circuit located adjacent the intersection of the “spine” and “arm” section of the chip for providing control signals to the at least one generator indicating load changes caused by the circuits in the adjacent sections of the chip;
• and
• (d) altering a generated voltage of the at least one generator to maintain a predetermined power level on the power bus in response to load changes caused by the circuits in the adjacent sections of the chip.