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US 6,310,506 B1Granted
Programmable setup/hold time delay network
AssigneeTexas Instruments Incorporated
InventorDavid R. Brown
Life of this patent
Estimating the term…
Abstract
A system and method for providing a programmable delay to an input signal in a device requiring setup and hold times for input signal, such as a DRAM device. In one embodiment, the programmable delay network 5 comprises a plurality of delay devices and at least one fuse connected between the input of the delay network 5 and the output of the delay network 5. Each fuse can connect in series with at least one delay device in such a manner that opening a fuse, or a combination of fuses, changes the amount of delay time the input signal experiences through the delay network.
Claims67
A signal latching apparatus for an integrated circuit, comprising:
- an input buffer connected to an input pin of the integrated circuit and operable to receive an externally applied input signal having a setup/hold time window from the input pin;
- a latching device operable to latch a signal at its input in response to an edge of a latching signal;
- and
- a delay network coupled to the input buffer and the latching device and operable to delay the input signal, the delay network comprising:
- a plurality of delay devices through which the input signal travels;
- and
- at least one fuse connected to at least one of the plurality of delay devices such that opening the fuse changes the amount of delay time the input signal experiences through the delay network such that the setup/hold time window of the delayed input signal at the input of the latching device coincides with the edge of the latching signal.
4 more elements
A programmable method for latching an input signal to a DRAM, the method comprising:
- manufacturing a DRAM;
- building a delay network into the DRAM to delay the input signal during operation;
- programming the delay network to adjust the amount of time the delay network delays the input signal so that the input signal coincides with an edge of a latching signal at a latch allowing the input signal to be latched in response to the edge of the latching signal.
Programmable input signal delay apparatus for an integrated circuit comprising:
- a latch circuit having an input, the latch circuit receiving an input signal at its input and latching the input signal in response to an edge of a latch signal, the input signal having a setup/hold time window from an input terminal of the integrated circuit;
- and
- a delay network having and input and an output, the output of the delay network coupled to the input of the latch circuit, the delay network comprising:
- at least one delay device coupled to the path through which the input signal travels, the at least one delay device operable to delay the time required for the input signal to arrive at the latch circuit;
- and
- at least one time delay adjustment mechanism, comprising at least one fuse, coupled to the at least one delay device, and wherein the time delay adjustment mechanism is operable to change the amount of delay time the input signal experiences through the delay network such that the setup/hold time window of the input signal at the input of the latch circuit coincides with the edge of the latch signal.
3 more elements
Programmable input signal delay apparatus for an integrated circuit comprising:
- an input buffer having an input and an output, the input buffer connected to an input pin of the integrated circuit and receiving an input signal externally applied to the input pin of the integrated circuit and providing a buffered input signal at its output, the input signal having a setup/hold time window at the input pin of the integrated circuit;
- a delay circuit having an input and an output, and comprising a time delay adjustment mechanism to adjust the delay associated with the delay circuit, the input of the delay circuit being coupled to the output of the input buffer such that the delay circuit receives the buffered input signal from the input buffer and delays the time required for the buffered input signal to propagate from the input of the delay circuit to the output of the delay circuit;
- and
- a latch circuit having an input coupled to the output of the delay circuit and receiving the delayed buffered the setup/hold time of the delayed buffered input signal at the input of the latch circuit coinciding with the edge of a latch signal such that the latch circuit latches the delayed buffered input signal in response to the edge of the latch signal.
1 more element
Programmable input signal delay apparatus for an integrated circuit comprising:
- a latch circuit having an input for receiving a buffered input signal, the latch circuit latching the buffered input signal in response to an edge of a latch signal;
- and
- a delay network having an input coupled to an input of the integrated circuit and an output, the delay network receiving an input signal applied to the input of the integrated circuit, the delay network comprising:
- at least one delay device coupled to the path through which the input signal travels, the at least one delay device operable to delay the time required for the input signal to propagate from the input of the delay circuit to the output of the delay circuit;
- and
- at least one time delay adjustment mechanism coupled to the at least one delay device;
- and
- an input buffer having an input coupled to the output of the delay network and an output, the input buffer receiving the input signal at its input and providing the buffered input signal at its output.
5 more elements
Dependencies are inferred from the claim text.