Semiconductor integrated circuit, delay-locked loop having the same circuit, self-synchronizing pipeline type system, voltage-controlled oscillator, and phase-locked loop

A semiconductor integrated circuit comprising a circuit unit, said circuit unit comprising:

• first and second capacitor means connected in parallel at one terminal of each capacitor means, the other terminal of the first capacitor means being an input terminal and the other terminal of the second capacitor means being a control terminal;
• a first transistor whose gate electrode is connected to the one terminals of the first and second capacitor means;
• a second transistor whose source terminal is connected to a source terminal of the first transistor;
• a third transistor drain terminal is connected to a drain terminal of the first transistor, said third transistor having a gate terminal and the drain terminal shorted;
• a fourth transistor forming a current mirror circuit with the third transistor;
• a fifth transistor whose drain terminal is connected to a drain terminal of the second transistor, said fifth transistor having a gate terminal and the drain terminal shorted;
• a sixth transistor forming a current mirror circuit with the fifth transistor;
• a seventh transistor whose drain terminal is connected to a drain terminal of the sixth transistor, said seventh transistor having the drain terminal and a gate terminal shorted;
• and
• an eighth transistor forming a current mirror circuit with the seventh transistor,
• wherein a drain terminal of the fourth transistor and a drain terminal of the eighth transistor are connected to each other to be connected to the gate electrodes of said NMOS transistor and said PMOS transistor.

A semiconductor integrated circuit comprising:

• a plurality of stages each comprising a circuit unit and an inverter connected to an output terminal of said circuit unit,
• wherein said circuit unit comprises an NMOS transistor and a PMOS transistor of which gate electrodes are connected commonly, and of which drain terminals are connected commonly, and
• wherein said circuit unit further comprises first and second capacitor means of which one terminals are commonly connected to the commonly connected gate electrodes of said NMOS and PMOS transistors,
• wherein the other electrode of said first capacitor means is an input terminal, and the other terminal of said second capacitor means is a control terminal,
• wherein a source terminal of said NMOS transistor is a ground terminal, a source terminal of said PMOS transistor is a power source terminal, commonly connected drain terminals of said NMOS and PMOS transistors are an output terminal, and
• wherein an output terminal of said inverter connected to said circuit unit in a prior stage is connected to the input terminal of said circuit unit in the next stage.

A voltage-controlled oscillator comprising a plurality of stages each comprising circuit unit each having an NMOS transistor, a PMOS transistor, a first capacitor means and a second capacitor means,

• in said circuit unit, gate electrode of said NMOS transistor is electrically connected to a gate electrode of said PMOS transistor, a drain of said NMOS transistor and a drain of said PMOS transistor are electrically connected and are used as an output terminal, a source terminal of said NMOS transistor is grounded, and a source terminal of said PMOS transistor is connected to a power source, and the gate electrodes of said NMOS transistor and said PMOS transistor are respectively connected to one electrodes of said first capacitor means and said second capacitor means, the other terminal of said first capacitor means is an input terminal for inputting a signal, and the other terminal of said second capacitor means is a control terminal for controlling a delay quantity of the signal;
• and
• an output terminal of said circuit unit in a prior stage in the plural stage is electrically connected to an input terminal of said circuit unit in the next stage, an output terminal of the final stage in the plural stage is electrically connected to an input terminal of a first stage and to an output section, control terminals of odd number order stages among the plural stages are commonly connected, and control terminals of even number order stages among the plural stages are commonly connected.