Methods and apparatus for adjusting the deadtime between non-overlapping clock signals

A method for changing the duty cycle of a clock signal, comprising:

• a) providing a clock gater circuit comprising first and second clock inputs;
• a clock output;
• a falling clock edge generation circuit coupled between the first clock input and the clock output, said falling clock edge generation circuit comprising a feed-forward path and a feedback path;
• and a rising clock edge generation circuit coupled between the second clock input and the clock output, said rising clock edge generation circuit comprising a feed-forward path and a feedback path;
• wherein the feed-forward path of one of the clock edge generation circuits comprises an even number more inverters than the feed-forward path of the other clock edge generation circuit;
• b) sizing one or more of the inverters to thereby affect a change in the duty cycle of a clock signal produced at said clock output.

Circuitry for producing non-overlapping clocks with a desired deadtime, comprising:

• a) a first clock gater circuit, comprising:
• i) one or more inputs for receiving a clock signal;
• and
• ii) an output for producing a first gated clock signal;
• and
• b) a second clock gater circuit, comprising:
• i) first and second inputs for receiving said clock signal;
• ii) an output for producing a second gated clock signal;
• iii) a falling clock edge generation circuit coupled between the first clock input and the clock output, said falling clock edge generation circuit comprising a feed-forward path and a feedback path;
• and
• iv) a rising clock edge generation circuit coupled between the second clock input and the clock output, said rising clock edge generation circuit comprising a feed-forward path and a feedback path;
• wherein the feed-forward path of one of the second clock gater circuit's clock edge generation circuits comprises an even number more inverters than the feed-forward path of the second clock gater circuit's other clock edge generation circuit, whereby adjustments in one or more of the inverters change a deadtime between the first and second gated clock signals.