Digital phase selection circuitry and method for reducing jitter

Apparatus comprising:

• a first phase detector having first and second inputs and an output, the first input being adapted to receive a reference frequency (fref) signal and the second input being adapted to receive a second signal, said first phase detector producing a signal at its output which is applied to a charge pump circuit for controlling a charge pump output current which is supplied to a filter circuit for developing a control voltage which is applied to a voltage controlled oscillator (VCO), the VCO for producing a number of clock signals having the same frequency but different phases;
• means for receiving data input signals;
• and
• circuitry coupled to receive said number of clock signals and including a second phase detector responsive to said data input signals and to a predetermined one of the clock signals of the VCO for producing a control signal for selectively coupling a selected one of the clock signals from the VCO to the second input of the first phase detector.

Apparatus comprising:

• a first phase detector having a first input adapted to receive a reference frequency (fref) signal and a second input adapted to receive a feedback signal and having an output coupled to a charge pump circuit for controlling a charge pump output current supplied to a filter circuit for developing a control voltage which is applied to a voltage responsive circuit, the voltage responsive circuit producing a predetermined number of clock signals whose frequency and phase vary as a function of the control voltage, and the predetermined number of clock signals having the same frequency, with each clock signal being delayed by a fixed time delay relative to each other;
• a multiplexer having an input port for receiving the predetermined number of clock signals and the multiplexer being responsive to a control signal for selectively coupling one of the predetermined number of clock signals to the second input of the first phase detector;
• and
• a second phase detector;
• means for applying an incoming data signal to said second phase detector and a selected one of said clock signals to said second phase detector whereby said second phase detector is responsive to said incoming data signal and to said selected one of the clock signals for producing said control signal.

Apparatus comprising:

• a phase detector having a first input adapted to receive a reference frequency (fref) signal and a second input adapted to receive a feedback signal and said phase detector having an output coupled to a charge pump circuit for controlling a charge pump output current supplied to a filter circuit for developing a control voltage which is applied to a voltage responsive circuit, the voltage responsive circuit, in response to the control voltage, producing a predetermined number of clock signals having the same frequency, with each clock signal being delayed relative to any other clock signal by a fixed time delay which is a function of the control voltage;
• a multiplexer for receiving the predetermined number of clock signals and responsive to a control signal for coupling one of the predetermined number of clock signals to the second input of the phase detector;
• and
• circuitry responsive to a data signal and to a preselected clock signal from the voltage responsive circuit for producing the control signal supplied to the multiplexer.

Apparatus comprising:

• a voltage responsive circuit for producing a number of different clock signals having the same frequency with each different clock signal being delayed relative to any other clock signal by a certain time delay which is a function of an amplitude of a control voltage applied to the voltage responsive circuit;
• a multiplexer for receiving a number of said different clock signals and having an output for, in response to a control signal, coupling a selected one of said different clock signals to the multiplexer output;
• a first phase detector responsive to a reference signal and to the output of the multiplexer for producing an error signal applied to a charge pump circuit for controlling a charge pump output current supplied to a filter circuit for developing the control voltage applied to the voltage responsive circuit;
• and
• a second phase detector responsive to data input signals and to a predetermined one of said different clock signals for producing the control signal applied to said multiplexer.

A method for producing a low jitter clock signal comprising the steps of:

• producing X clock signals having the same frequency but with different phases;
• where X is an integer greater than one (1);
• selectively selecting different ones of said X clock signals as a function of comparing an incoming data stream and a preselected one of the X clock signals and comparing the selected clock signals with a reference signal for producing an error signal indicative of a phase difference between the selected clock signal and the reference signal;
• changing at least one of the phase and frequency of the X clock signals as a function of the amplitude and polarity of the error signal;
• and
• comparing a preselected one the X clock signals with said incoming data stream for sensing the frequency of incoming data stream and for sampling the contents of the data stream.

A method for producing a low jitter clock signal comprising the steps of:

• applying a control voltage to a voltage responsive circuit for producing X different clock signals having the same frequency with each different clock signal being delayed relative to any of the other clock signal by an amount which is a function of the control voltage;
• where X is an integer greater than one (1);
• selectively selecting different ones of said X clock signals in response to a control signal;
• comparing the selected clock signal with a reference signal for producing an error signal indicative of a phase difference between the selected clock signal and the reference signal and for producing the control voltage to be applied to the voltage responsive circuit;
• and
• comparing a preselected one of the X clock signals with an incoming data stream for sensing the frequency of the incoming data stream and producing the control signal.

Apparatus comprising:

• a voltage responsive circuit for producing X different clock signals, where X is an integer greater than one (1), each one of said X clock signals having the same frequency and a different phase,
• means for applying a control voltage to the voltage responsive means wherein the phase of each one of the X clock signals varies as a function of an amplitude of the control voltage applied to the voltage responsive circuit;
• a selection circuit for receiving said X clock signals and having an output, said selection circuit being responsive to a control signal for coupling a selected one of said X clock signals to the selection circuit output;
• circuitry for comparing a designated one of the X clock signals with a data input stream for producing said control signal as a function of a difference and for applying said control signal to said selection circuit;
• and
• circuitry responsive to the output of said selection circuit and to a reference frequency signal for producing said control voltage which is a function of a difference between the signal at the output of the selection circuit and the reference frequency signal.