Signal transition accelerating driver circuit for promptly driving bus line and bus driving system using the same

A signal driving circuit comprising:

• an output driver driving a signal line in response to first and second control signals (CTL 1 and CTL 2) for selectively connecting respective first and second sources of potential to the signal line;
• a controller having first and second operation modes, the controller in the first mode selectively producing the first and second control signals in response to a data signal, the controller in the second mode selectively producing the first and second control signals in response to a signal line potential and not in response to the data signal, to accelerate change of the signal line potential;
• a timer, implemented as one of a delay flip-flop and a shift register, responsive to a pulse signal limiting a duration of production of the first and second control signals by the controller in the second mode;
• and
• a pulse generator connected between the signal line and the timer for producing the pulse signal in response to variation of the signal line potential.

A driver system for changing a potential level on a signal line, comprising:

• a first driver circuit including a first output driver driving a signal line in response to first and second control signals (CTL 1 and CTL 2) for selectively connecting respective sources of potential to the signal line, a first controller having first and second operation modes, the first controller in the first mode selectively producing the first and second control signals (CTL 1 and CTL 2) in response to a first data signal, the first controller in the second mode selectively producing said first and second signals in response to a first signal line potential to accelerate change of the first signal line potential, and a first timer responsive to a first pulse signal limiting a duration of production of said first and second control signals (CTL 1 and CTL 2) by the first controller in the second mode;
• a second driver circuit including a second output driver driving the signal line in response to third and fourth control signals for selectively connecting the respective sources of potential to the signal line, a second controller having first and second operation modes, the second controller in the first mode selectively producing the third and fourth control signals in response to a second data signal, the second controller in the second mode selectively producing third and fourth signals in response to a second signal line potential to accelerate change of the second signal line potential, and a second timer responsive to a second pulse signal limiting a duration of production of said third and fourth control signals by the second controller in the second mode;
• and
• a third driver circuit including a third output driver driving the signal line in response to fifth and sixth control signals for selectively connecting respective sources of potential to the signal line, a third controller operating exclusively in the second operation mode to selectively produce fifth and sixth signals in response to a third signal line potential to accelerate change of the third signal line potential, and a third timer responsive to a third pulse signal limiting a duration of production of said fifth and sixth control signals by the third controller in the second mode.