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AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsHeiji Ikoma, Yoshitsugu Inagaki, Hiroyuki Konishi, Koji Oka, Akira Matsuzawa
Estimating the term…
In order to reduce power consumption, a power supply for a digital circuit portion is shut off, so that the output voltage of the power supply becomes the zero level. A CMOS (complementary metal oxide semiconductor) inverter has a P-channel FET (field effect transistor) with a gate electrode formed of P-type polysilicon. A source electrode of the P-channel FET is connected to the power supply and a back gate electrode of the P-channel FET is in direct connection with the aforesaid source electrode. The P-channel FET is placed in a state of not functioning as a transistor when the power supply is shut off in a low power consumption mode. However, in order to prevent the P-channel FET from undergoing characteristic degradation in that mode, there is the provision of a pull-down switch capable of fixing, in the mode, the voltage of the gate electrode of the P-channel FET at the zero level.
A semiconductor integrated circuit comprising a P-channel field effect transistor (FET) which has a drain electrode, a source electrode, a gate electrode formed of a P-type semiconductor material, and a back gate electrode and which is configured such that in a normal operation mode (a) a certain voltage is supplied from a power supply to said source electrode and (b) another voltage representative of an input signal is supplied to said gate electrode,
The semiconductor integrated circuit according to claim further comprising a detection circuit operable to detect a state in which said power supply is shut off for asserting said control signal.
Dependencies are inferred from the claim text.