Method to reduce wire-or glitch in high performance bus design to improve bus performance
AssigneeSun Microsystems, Inc.
InventorsLeo Yuan, Christopher Cheng
Life of this patent
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Abstract
A system and method of reducing wire-or glitch to improve bus speeds. In a system that supports wire-or functions, the rise time of the wave created by the off-going driver is controlled. The off-going wave is forced to climb gradually such that one propagation delay of the loaded bus later, it is only marginally above a high threshold voltage. The fall time of the wave created by an on-going driver is minimized such that a strong negative going voltage propagates down the bus. This strong negative going voltage drags a composite wave on the bus (i.e. the combination of the waves of the on-going driver and the off-going driver) back below a low threshold voltage approximately one propagation delay after the switching occurs.
Claims10
A method of improving a system cycle time in a system implementing wire-or function comprising the step of:
- reducing a wire-or glitch so that a bus can be sampled after a single trip propagation delay.
A system supporting wire-or functions comprising:
- a plurality of drivers disposed along a bus, the drivers having a gradual rise time and rapid fall time such that for any pair of simultaneously switching drivers along the bus, a falling signal will propagate to a rising signal before the rising signal reaches a predetermined level;
- and
- a first terminal resistor and second terminal resistor coupled to a first end and a second end of the bus, respectively.
Dependencies are inferred from the claim text.