Integrated circuit device having a burn-in mode for which entry into and exit from can be controlled
AssigneeSTMicroelectronics S.r.l.
InventorDavid Charles McClure
Life of this patent
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Abstract
An integrated circuit structure and method provides a burn-in stress test mode that facilitates stress testing of an integrated circuit device in a burn-in oven. The integrated circuit structure and method is capable of disabling a time-out feature of an IC memory device during a stress test mode of the device in order to facilitate stress testing of the device in a burn-in oven. The integrated circuit structure provides for entry into the burn-in stress test mode when a supply voltage supplied to the integrated circuit device exceeds a predetermined voltage level and/or the temperature of the integrated circuit device exceeds a predetermined temperature level.
Claims19
A burn-in stress test mode circuit of an integrated circuit device, comprising:
- a diode stack comprised of a plurality of diodes , wherein the plurality of diodes are serially connected with a first diode of the plurality of diodes connected to a first supply voltage;
- a first transistor having a gate connected to the first supply voltage;
- a second transistor having a gate controlled by a power-on reset signal;
- and
- a first logic element having an input terminal and an output terminal, wherein a node is defined by the electrical connection of the input terminal of the first logic element, a second diode of the plurality of diodes of the diode stack, a second source/drain of the first transistor, and a second source/drain of the second transistor;
- wherein when the first supply voltage of the integrated circuit device exceeds a predetermined voltage level equal to a diode forward bias voltage drop of the diode stack plus a voltage trip point of the first logic element, the integrated circuit device enters a burn-in mode.
Dependencies are inferred from the claim text.