Semiconductor die assembly having leadframe decoupling characters

An semiconductor die assembly comprising:

• a semiconductor die having at least one integrated circuit therein, having a first active surface having, in turn, at least one bond pad arranged thereon, and having a second surface;
• an upper conductive planar leadframe member having an upper surface mounted to at least a portion of said second surface of said semiconductor die using an intervening electrically insulative adhesive, and having a lower surface, said upper conductive planar leadframe member subdivided into a plurality of portions;
• a lower conductive planar leadframe member having an upper surface mounted to the lower surface of said upper conductive planar leadframe member using a thin intervening layer of dielectric material for capacitance resulting therebetween, said lower conductive planar leadframe member subdivided into a plurality of portions, at least one portion of said plurality of portions having an exposed tab connected to said at least one integrated circuit of said semiconductor die, said lower conductive planar leadframe member
• cooperating with said upper conductive planar leadframe member for capacitance purposes;
• at least one lead of a plurality of leads connecting said at least one bond pad to at least one lead finger;
• and
• at least one other lead of said plurality of leads connected to said exposed tab of said lower conductive planar leadframe member.

An semiconductor die assembly comprising:

• a housing;
• a semiconductor die located in said housing, said semiconductor die having at least one integrated circuit therein, said semiconductor die having a first surface having, in turn, at least one bond pad arranged thereon and having a second surface, said at least one integrated circuit of said semiconductor die subject to transient electrical coupling and noise generation;
• an upper conductive planar leadframe member having an upper surface attached to at least a portion of said second surface of said semiconductor die using an intervening electrically insulative adhesive, and having a lower surface, said upper conductive planar leadframe member subdivided into multiple portions, said upper conductive planar leadframe member subdivided into a plurality of coplanar portions representing individual capacitors, at least one portion of said multiple portions having an exposed tab connected to said at least one integrated circuit;
• a lower conductive planar leadframe member having an upper surface mounted to the lower surface of said upper conductive planar leadframe member using a thin intervening layer of dielectric material, said lower conductive planar leadframe member subdivided into a plurality of coplanar portions representing individual capacitors, said lower conductive planar leadframe member cooperating with said upper conductive planar leadframe member for capacitance purposes;
• at least one lead of a plurality of leads connecting said at least one bond pad to at least one lead finger;
• and
• at least one other lead of said plurality of leads connected to said exposed tab of said upper conductive planar leadframe member and across portions of said at least one integrated circuit of said semiconductor die subject to said transient coupling and noise generation.

A semiconductor die assembly comprising:

• a housing;
• a semiconductor die located in said housing, said semiconductor die having an integrated circuit therein, said semiconductor die having a first surface having, in turn, a plurality of bond pads arranged thereon and having a second surface, said integrated circuit of said semiconductor die subject to transient electrical coupling and noise generation;
• an upper conductive planar leadframe member having an upper surface attached to at least a portion of said second surface of said semiconductor die using an intervening electrically insulative adhesive, and having a lower surface, said upper conductive planar leadframe member subdivided into a plurality of coplanar portions representing individual capacitors;
• a lower conductive planar leadframe member having at least a portion of an upper surface mounted to the lower surface of said upper conductive planar leadframe member using a thin intervening layer of dielectric material for the capacitance therebetween, said lower
• conductive planar leadframe member subdivided into multiple portions, at least one of said multiple portions having an exposed tab connected to said integrated circuit and having tailored operating capacitance/frequency characteristics in cooperation with the upper conductive planar leadframe member;
• at least one lead connecting at least one bond pad of said plurality of bond pads to at least one lead finger;
• and
• at least one other lead connected to said exposed tab of said lower conductive planar leadframe member and across portions of said integrated circuit of said semiconductor die subject to said transient coupling and noise generation.

A semiconductor die assembly comprising:

• a housing;
• a semiconductor die located in said housing, said semiconductor die having an integrated circuit therein, said semiconductor die having a first surface having, in turn, a plurality of bond pads arranged thereon and having a second surface for mounting said semiconductor die, said integrated circuit of said semiconductor die subject to transient electrical coupling and noise generation;
• an upper conductive leadframe member having an upper surface mounted to at least a portion of said second surface of said semiconductor die using an intervening electrically insulative adhesive, and a lower surface;
• a lower conductive leadframe member having an upper surface mounted to the lower surface of said upper conductive leadframe member using a thin intervening layer of dielectric material for capacitance therebetween;
• leads connecting some of said plurality of bond pads to lead fingers;
• leads connected to said upper and lower conductive leadframe members and across portions of said integrated circuit of said semiconductor die subject to said transient coupling and noise generation;
• wherein each of said upper and lower conductive leadframe members subdivided into multiple portions, at least one of said multiple portions having at least one exposed tab connected to said integrated circuit and having tailored operating capacitance/frequency characteristics in cooperation with the each subdivided upper and lower conductive leadframe member.

A method for making a semiconductor die package having a semiconductor die having an active surface having at least one bond pad thereon and a support surface, said method comprising:

• forming a multi-level conductive leadframe having a lower leadframe portion and an upper leadframe portion partially coextensive therewith, said upper and lower leadframe portions each having upper and lower surfaces, said upper surface of said upper leadframe portion configured to be bonded to at least a portion of the support surface of said semiconductor die, said upper leadframe portion subdivided into a plurality of units, said lower leadframe portion subdivided into a plurality of units, one of said upper leadframe portion and said lower leadframe portion having at least one outwardly extending conductive tab one of said lower and upper leadframe portions having centrally directed inner leads;
• providing a dielectric material;
• joining an upper surface of at least one of the plurality of units of said subdivided lower leadframe portion to a lower surface of one of the plurality of units of said subdivided upper leadframe portion using an intervening layer of said dielectric material, each of the plurality of units formed by the upper leadframe portion and the plurality of units formed by the lower leadframe portion and said intervening layer of dielectric material comprising a capacitor;
• providing an insulative material;
• bonding at least a portion of the support surface of said semiconductor die to the upper surface of the subdivided upper leadframe portion using said insulative material;
• lancing the upper and lower leadframe portions to singulate inner leads therefrom;
• bonding at least one conductive wire between the at least one bond pad on the active surface of the semiconductor die and at least one inner lead of the inner leads, the at least one outwardly extending conductive tab of said one of the subdivided upper leadframe portion and the lower leadfrarne portion;
• encapsulating the semiconductor die, the inner leads, a plurality of capacitors, and said at least one conductive wire in a package;
• and
• lancing external lead portions to form outer leads for connecting the semiconductor die package to an electronic apparatus.