Electrostatic discharge protection transistor structure with a trench extending through the source or drain silicide layers

An electrostatic discharge protection transistor comprising:

• a semiconductor p-substrate, the semiconductor p-substrate having n+ source and n+ drain diffusion regions, the semiconductor p-substrate having respective source and drain n-wells under the n+ source and n+ drain diffusion regions, the semiconductor p-substrate having lightly doped regions in the source and drain n-wells;
• a gate formed over the semiconductor p-substrate covering portions of the lightly doped n+ source and n+ drain junctions;
• source and drain suicides respectively formed on the n+ source and n+ drain diffusion regions;
• n+ source and n+ drain contacts respectively connected to the source and drain suicides;
• and
• a drain trench in the semiconductor p-substrate separating the drain silicide between the n+ drain contact and the gate, the drain trench extending through the n+ drain diffusion region into the drain n-well.

An electrostatic discharge protection transistor comprising:

• a semiconductor p-substrate, the semiconductor p-substrate having n+ source and n+ drain diffusion regions, the semiconductor p-substrate having respective source and drain n-wells under the n+ source and n+ drain diffusion regions, the semiconductor p-substrate having lightly doped regions in the source and drain n-wells;
• a gate formed over the semiconductor p-substrate covering portions of the lightly doped n+ source and n+ drain junctions;
• source and drain silicides respectively formed on the n+ source and n+ drain diffusion regions;
• n+ source and n+ drain contacts respectively connected to the source and drain suicides;
• and
• a source trench in the semiconductor p-substrate separating the source silicide between the n+ source contact and the gate, the source trench extending through the n+ source diffusion region into the source n-well.