Semiconductor processing methods of forming a conductive projection and methods of increasing alignment tolerances

A method of forming DRAM circuitry comprising:

• forming a conductive plug over a substrate node location between a pair of conductive lines and with which electrical communication with a bit line is desired, the conductive plug having a first uppermost surface;
• unevenly doping material of the conductive plug with dopant proximate the uppermost surface, outermost side portions of the plug having greater concentrations of dopant than plug material therebetween;
• and
• unevenly removing material from the first uppermost surface of the conductive plug to define an uneven second uppermost surface at least a portion of which is disposed elevationally higher than the conductive lines and to reduce a width of the conductive plug from what it was prior to said unevenly removing, the unevenly removing comprising etching material of the conductive plug containing greater concentrations of dopant at a greater rate than material of the conductive plug containing lower concentrations of dopant.

A method of forming DRAM circuitry comprising:

• forming a conductive plug over a substrate node location between a pair of conductive lines and with which electrical communication with a bit line is desired, the conductive plug having a first uppermost surface having a generally uniform surface and having a width;
• unevenly doping material of the conductive plug with dopant proximate the uppermost surface, outermost side portions of the plug having greater concentrations of dopant than plug material therebetween;
• and
• etching material of the conductive plug to define a second uppermost surface which is generally non-planar and at least a portion of which is disposed elevationally higher than the conductive lines and to reduce the width of the conductive plug, the etching comprising etching material of the conductive plug containing greater concentrations of dopant at a greater rate than material of the conductive plug containing lower concentrations of dopant.

A method of forming DRAM circuitry comprising:

• forming insulative material over the node location;
• forming a contact opening through the insulative material and exposing a portion of the node location;
• forming conductive material within the contact opening the conductive material forming a conductive plug over a substrate node location between a pair of conductive lines and with which electrical communication with a bit line is desired, the conductive plug having a first uppermost surface having a generally uniform surface and having a width;
• etching material of the conductive plug to define a second uppermost surface which is generally non-planar and at least a portion of which is disposed elevationally higher than the conductive lines and to reduce the width of the conductive plug;
• and
• removing said insulative material prior to etching material of the conductive plug.

A method of forming DRAM circuitry comprising:

• forming a conductive plug over a substrate node location between a pair of conductive lines and with which electrical communication with a bit line is desired, the conductive plug having an uppermost surface which is defined in part by a corner region and having a width;
• providing impurity into the corner region;
• and
• etching material of the conductive plug containing greater concentrations of the impurity at a greater rate than material of the conductive plug containing lower concentrations of the impurity effective to reduce the width of the conductive plug.

A semiconductor processing method of forming a conductive projection comprising:

• providing a substrate having a surface area over which a conductive projection is to be formed;
• forming a conductive projection over the surface area, the projection having an upper surface and a side surface joined therewith defining a corner region;
• beveling the corner region of the conductive projection;
• wherein the surface area comprises a diffusion region, and further comprising after the beveling of the corner region, forming conductive material over the beveled corner region of the conductive projection and in electrical communication with the diffusion region;
• and further comprising BPSG being received against the side surface at the corner region at the start of the beveling.

A semiconductor processing method of forming a conductive projection comprising:

• providing a substrate having a surface area over which a conductive projection is to be formed;
• forming a conductive projection over the surface area, the projection having an upper surface and a side surface joined therewith defining a corner region;
• beveling the corner region of the conductive projection;
• and
• wherein the beveling of the corner region comprises:
• unevenly doping material of the conductive projection proximate the upper and side surfaces thereof;
• etching material of the conductive projection containing greater concentrations of dopant at a greater rate than material of the conductive projection containing lower concentrations of dopant;
• and
• further comprising BPSG being received against the side surface at the corner region at the start of the beveling.

A semiconductor processing method of forming a conductive projection comprising:

• forming a pair of spaced-apart, insulated conductive lines over a substrate, the conductive lines defining a node location therebetween with which electrical communication is desired;
• forming insulative material over the node location and between the conductive lines;
• forming an opening through the insulative material and between the lines to proximate the node location;
• forming conductive material within the opening over the node location, the conductive material having side surfaces which project away from the node location and terminate proximate an upper surface, the side surfaces and upper surface defining at least one corner region;
• beveling the corner region;
• further comprising BPSG being received against at least one side surface at the corner region at the start of the beveling;
• and
• planarizing said conductive material to be substantially coplanar with the second layer surface.