US 6,309,957 B1 · Method of low-K/copper dual damascene

Abstract

This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to both dual and single inverse copper damascene processes to form conducting copper interconnects and contact vias simultaneously, with low dielectric constant intermetal dielectrics (IMD). The low dielectric constant material, low-K, can be of four types of material: doped oxide, organic materials, highly fluorinated films, porous materials. In addition, spin-on glass (SOG) and spin-on-dielectric (SOD) are applicable. Key to the present invention are the following process steps, that have exceptionally advanced process controls: polysilicon etching of sacrificial polysilicon, plasma ashing of the patterning photoresist, and post cleaning. With conventional dual damascene, wherein dielectric material is patterned into dual damascene, several deleterious effects occur: (1) etching of low-K material can be difficult and can affect the electrical properties, (2) photoresist ashing can impact both the dielectric constant of low-K material and critical dimensional bias control, (3) post cleaning can impact the dielectric constant of low-K material. Using both the inverse dual and single damascene processes disclosed by this invention, the problems associated with convention damascene approaches are circumvented.

Claims26

Dependent claims

A method for fabricating conductive inlaid copper interconnects and contact vias for applications in MOSFET and CMOS semiconductor devices using an inverse copper dual damascene comprising:

providing a substrate over which is formed an interlevel dielectric;
forming a first level of conductive wiring over said interlevel dielectric;
forming an insulating layer around said first level of conductive wiring and over interlevel dielectric;
forming sacrificial polysilicon islands over said first level of conducting wiring and insulating layer;
depositing low dielectric material over said sacrificial polysilicon islands and insulating layer;
planarizing the excess said sacrificial polysilicon islands and excess said low dielectric material;
forming sacrificial polysilicon lines over said polysilicon islands and said low dielectric material;
depositing a layer of low dielectric material over said sacrificial polysilicon lines and low dielectric;
planarizing the excess said sacrificial polysilicon lines and excess said layer of low dielectric material;
removing all of the said sacrificial polysilicon lines and islands forming dual damascene, trench interconnect and contact via openings;
filling said interconnect and via with inlaid copper, planarizing surface to remove excess metal.

8 more elements

A method for fabricating conductive inlaid interconnects and contact vias for applications in semiconductor devices using an inverse dual damascene process comprising:

providing a substrate over which is formed an interlevel dielectric;
forming a first level of conductive wiring over said interlevel dielectric;
forming an insulating layer around said first level of conductive wiring and over interlevel dielectric;
forming islands consisting of sacrificial material over said first level of conducting wiring and said insulating layer;
forming a first layer of low dielectric constant material around and over said islands and over said insulating layer;
removing the excess said sacrificial material and excess said low dielectric constant material to planarize the surface;
forming lines consisting of sacrificial material over said islands and said first layer of low dielectric constant material;
forming a second layer of low dielectric constant material around and over said lines and over the first layer of low dielectric constant material;
removing the excess said sacrificial material and excess said low dielectric material to planarize the surface;
removing all of the said sacrificial material, lines and islands, to form dual damascene, trench interconnect and contact via openings;
filling said interconnect and via openings with inlaid conducting material, planarizing the surface to remove excess conductive material.

8 more elements

Dependencies are inferred from the claim text.

Method of low-K/copper dual damascene

Life of this patent

Method of low-K/copper dual damascene

Life of this patent

Abstract

Claims26