Reduced RC delay between adjacent substrate wiring lines

A method for providing a void in a spacing between adjacent wiring lines of a semiconductor substrate, the method comprising:

• depositing at least three conductive layers over the semiconductor substrate comprising a lower layer, a middle layer and an upper layer;
• subsequently configuring said at least three conductive layers deposited over the semiconductor substrate into at least two adjacent elongated wiring lines, forming said lower layer and said middle layer of said at least three conductive layers to each have a lateral width less than a lateral width of said upper layer so that said at least two adjacent elongated wiring lines each have a cross-sectioned shape of a “T” and laterally extending tops extending substantially along the length of the at least two adjacent elongated wiring lines;
• depositing dielectric material on the substrate and the semiconductor at least two adjacent elongated wiring lines with the laterally extending tops to form a layer thereover;
• and
• causing the dielectric material to accumulate between edges of the laterally extending tops of the at least two adjacent wiring lines to seal off an elongated void area between the at least two adjacent elongated wiring lines.