US 6,309,929 B1Granted

Method of forming trench MOS device and termination structure

AssigneeIndustrial Technology Research Institute and Genetal Semiconductor of Taiwan, Ltd.

InventorsChih-Wei Hsu, Chung-Min Liu, Ming-Che Kao, Ming-Jinn Tsai, Pu-Ju Kung

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Abstract

A method for fabricating trench MOS devices and termination structure simultaneously is disclosed. The MOS devices can be Schottky diode, IGBT or DMOS depending on the semiconductor substrate prepared. The method comprises following steps: firstly, forming a plurality of first trenches for forming the trench MOS devices in an active region, and a second trench for forming the termination structure. Thereafter, a thermal oxidation process to form a gate oxide on all areas is performed. Then, the first trenches and the second trench are refilled with a first conductive material. An etching back is carried out to remove excess first conductive material so as to form spacer in the second trench and to fill the first trenches only. Next, the gate oxide layer is removed. For IGBT or DMOS device, an extra thermal oxidation and an etching step are required to form inter-conductive oxide layer whereas for Schottky diode, these two steps are skipped. Thereafter, a termination structure oxide layer is formed through deposition, lithographic process and etching. After backside unnecessary layers removal, a sputtering metal layers deposition, lithographic process and etching step are successively performed to form the first electrode with a desired ended location and the second electrode on both side of semiconductor substrate.

Claims25

Dependent claims

A method of fabricating trench MOS devices and termination structure simultaneously, said method comprising the steps of:

providing a semiconductor substrate;
forming a plurality of first trenches for forming said trench MOS devices in an active region of a semiconductor substrate, and a second trench for forming said termination structure from a boundary of said active region to a margin of said semiconductor substrate, said second trench and said first trench spaced by a mesa;
performing a thermal oxidation process so as to form a gate oxide on all areas of said semiconductor substrate;
refilling said plurality of first trenches and said second trench with a first conductive material;
performing an etching back process using a surface of said semiconductor substrate of said mesa as a stopping layer, and forming a spacer on a sidewall of said second trench;
removing said gate oxide layer using said surface of said semiconductor substrate of said mesa as a stopping layer;
forming a termination structure oxide layer on all areas of said semiconductor substrate;
forming a photoresist pattern on said termination structure oxide layer to define an insulating region and to expose a region from said active region to said spacer;
etching away said exposed region using said photoresist pattern as a mask;
stripping said photoresist pattern;
removing backside unnecessary layers of said semiconductor substrate so as to expose said semiconductor substrate;
forming a second conductive material on all areas of said semiconductor substrate;
forming a photoresist pattern on said second conductive material so as to define an electrode;
and
etching away exposed portion of said second conductive material so that said electrode is formed.

12 more elements

A method of fabricating trench MOS devices and termination structure simultaneously, said method comprising the steps of:

providing a semiconductor substrate;
forming a plurality of first trenches for forming said trench MOS devices in an active region of a semiconductor substrate, and a second trench for forming said termination structure from a boundary of said active region to a margin of said semiconductor substrate, said second trench and said first trench spaced by a mesa;
performing a thermal oxidation process so as to form a gate oxide on all areas of said semiconductor substrate;
forming a first conductive layer to refill said plurality of first trenches and said second trench with a first conductive material;
performing an etching back process using a surface of said semiconductor substrate of said mesa as a stopping layer, and forming a spacer on a sidewall of said second trench;
removing said gate oxide layer using said surface of said semiconductor substrate of said mesa as a stopping layer;
performing a thermal oxidation process so as to form inter-conductive oxide layer by consuming a portion of on said semiconductor substrate and a portion of said first conductive layer;
removing said inter-conductive oxide layer using said surface of said semiconductor substrate of said mesa as a stopping layer;
forming a termination structure oxide layer on all areas of said semiconductor substrate;
forming a photoresist pattern on said termination structure oxide layer to define an insulating region and to expose a region from said active region to said spacer;
etching away said exposed region using said photoresist pattern as a mask;
stripping said photoresist pattern;
removing backside unnecessary layers of said semiconductor substrate so as to expose said semiconductor substrate;
forming a second conductive material on all areas of said semiconductor substrate so as to form a first electrode and second electrode on upper side and back side surfaces, respectively;
forming a photoresist pattern on said second conductive material so as to define a position of said first electrode;
and
etching away exposed portion of said second conductive material so that said electrode is formed.

14 more elements

Dependencies are inferred from the claim text.