Split-gate flash cell

A method of forming a novel split-gate flash memory cell having a novel poly-tip comprising the steps of:

• providing a semiconductor substrate having active and passive regions defined;
• performing voltage threshold adjustment implantation;
• forming a gate oxide layer over said substrate;
• forming a first polysilicon layer over said gate oxide layer;
• forming a first nitride layer over said first polysilicon layer (poly-1);
• forming a shallow trench ST-photomask over said first nitride layer;
• forming a shallow trench in said substrate by etching said first nitride layer, first polysilicon layer, gate oxide layer and said substrate;
• removing said ST-photomask;
• depositing a first oxide layer over said substrate including said shallow trench;
• performing chemical mechanical polishing of said first oxide layer over said substrate;
• removing said first nitride layer;
• forming a second oxide layer over said substrate;
• depositing a second nitride layer over said second oxide layer;
• forming a poly-1 photomask over said second nitride layer;
• forming openings in underlying said second nitride layer, said second oxide layer and first polysilicon layer through patterns in said poly-1 photomask to form a floating gate structure;
• removing said poly-1 photomask;
• performing oxidation of said first polysilicon layer to form a novel poly-tip for said floating gate;
• forming a hot temperature oxide (HTO) layer over said substrate including said poly-tip and floating gate;
• forming a second polysilicon layer (poly-2) over said HTO layer;
• forming a poly-2 photomask over said second polysilicon layer;
• etching and patterning said second polysilicon layer through said poly-2 photomask to form a control gate;
• removing said poly-2 mask;
• forming a self-aligned source (SAS)-photomask over said substrate including said poly-2 layer;
• etching through said SAS-mask and removing said oxide in said shallow trench;
• performing ion implantation through said patterning in said second poysilicon layer to form source regions in said substrate;
• removing said SAS-mask;
• performing source drive;
• forming a conformal nitride layer over said substrate;
• forming nitride spacers;
• performing ion implantation to form drain regions in said substrate;
• forming interlevel dielectric layer over said substrate;
• forming contact holes in said interlevel dielectric layer;
• forming metal in said contact holes;
• and
• etching back excess metal over said substrate in preparation for performing the remaining process steps in the manufacture of said flash split-gate memory device.