Thin resist with nitride hard mask for gate etch application

A method of forming a gate, comprising:

• forming a nitride layer on a gate material layer, the nitride layer having a thickness within a range of 50 Å-500 Å;
• forming an ultra-thin photoresist layer on the nitride layer, the ultra-thin photoresist layer having a thickness within a range of 50 Å-1000 Å;
• patterning the ultra-thin photoresist layer with short wavelength radiation to define a pattern for the gate, the short wavelength radiation falling within a range about 11 nm to 13 nm;
• using the ultra-thin photoresist layer as a mask during a first etch step to transfer the gate pattern to the nitride layer, the first etch step including an etch chemistry that is selective to the nitride layer over the ultra-thin photoresist layer;
• and
• using the nitride layer as a hard mask during a second etch step to form the gate by transferring the gate pattern to the gate material via the second etch step.

A method for fabricating a memory cell structure, comprising:

• forming a first nitride layer on a first gate material layer, the first nitride layer having a thickness within a range of 50 Å-1000 Å;
• forming a first ultra-thin photoresist layer on the first nitride layer, the first ultra-thin photoresist layer having a thickness within a range of 50 Å-1000 Å;
• patterning the first ultra-thin photoresist layer with short wavelength radiation to define a pattern for floating gates, the short wavelength radiation being less than 100 nm;
• using the first ultra-thin photoresist layer as a mask during a first etch step to transfer the floating gate pattern to the first nitride layer, the first etch step including an etch chemistry that is selective to the first nitride layer over the first ultra-thin photoresist layer;
• and
• using the first nitride layer as a hard mask during a second etch step to form the floating gates by transferring the floating gate pattern to the first gate material via the second etch step;
• forming an interpoly dielectric layer over the floating gates;
• forming a second gate material over the interpoly dielectric layer;
• forming a second nitride layer on the second gate material layer, the second nitride layer having a thickness within a range of 50 Å-1000 Å;
• forming a second ultra-thin photoresist layer on the second nitride layer;
• patterning the second ultra-thin photoresist layer with short wavelength radiation to define a pattern for control gates, the short wavelength radiation being less than 100 nm;
• using the second ultra-thin photoresist layer as a mask during a third etch step including an etch chemistry that is selective to the second nitride layer over the second ultra-thin photoresist layer;
• and
• using the second nitride layer as a hard mask during a fourth etch step to form the control gates by transferring the control gate pattern to the second gate material layer via the fourth etch step.