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US 6,309,915 B1Granted
Semiconductor chip package with expander ring and method of making same
AssigneeTessera, Inc.
InventorThomas H. Distefano
Life of this patent
Estimating the term…
Abstract
A method of making a semiconductor chip assembly, including providing a dielectric element with a plurality of electrically conductive terminals, disposing an expander ring over the dielectric element so that a semiconductor chip on the dielectric layer is disposed in a central opening in the expander ring, and disposing an encapsulant in the gap between the expander ring and the semiconductor chip. The size of the gap is controlled to minimize the pressure exerted on the leads by the elastomer as it expands and contracts in response to changes in temperature. The semiconductor chip and expander ring may also be connected to a heat sink or thermal spreader with a compliant adhesive.
Claims14
A method of making a plurality of semiconductor chip assemblies, said method comprising the steps of:
- I. providing a dielectric element having a top surface and a plurality of electrically conductive traces, wherein each electrically conductive trace has a terminal-end, a contact-end opposite the terminal-end, and an electrically conductive terminal disposed at the terminal-end;
- II. disposing a compliant layer on the top surface of the dielectric element;
- III. providing a plurality of semiconductor chips, each of the semiconductor chips having a face surface, a plurality of electrically conductive contacts disposed on the face surface, and a plurality of side surfaces which define the outer perimeter of the semiconductor chip;
- IV. adhering the face surface of each semiconductor chip to the compliant layer;
- V. providing a strip of expander rings, each of the expanders rings having a plurality of inner side walls which define a central opening;
- VI. disposing the strip of expander rings over the top surface of the dielectric element such that
- a) each of the semiconductor chips is associated with one of the expander rings;
- b) each of the semiconductor chips is disposed within the central opening of the associated expander ring;
- and
- c) a gap is formed between the outer perimeter of each the semiconductor chips and the inner side walls of the associated expander ring;
- VII. forming at least one lead connecting each semiconductor chip to the dielectric element by connecting at least one contact on the face surface of each semiconductor chip to the contact-end of one of the traces;
- and
- VIII. encapsulating each of the semiconductor chip assemblies by filling the gap and open spaces between the dielectric element, the compliant layer, the semiconductor chip and the expander ring with a liquid composition which is curable to an encapsulant;
- wherein
- w≧{(CTEexpander ring−CTEchip)Xc}/{CTEencapsulant(1+2p)};
- where w is the width of each gap;
- CTEchip is the coefficient of thermal expansion of one of the semiconductor chips;
- CTEexpander ring is the coefficient of thermal expansion of the associated expander ring;
- Xc is the shortest distance between a point on the outer perimeter of the semiconductor chip and the center of the semiconductor chip;
- CTEencapsulant is the coefficient of thermal expansion of the encapsulant;
- and p is the Poisson ratio of the encapsulant.
18 more elements
A method of making a semiconductor chip assembly, said method comprising the steps of:
- I. providing a dielectric element having a top surface and a plurality of electrically conductive traces, wherein each electrically conductive trace has a terminal-end, a contact-end opposite the terminal-end, and an electrically conductive terminal disposed at the terminal-end;
- II. disposing a compliant layer on the top surface of the dielectric element;
- III. providing a semiconductor chip having a face surface, a plurality of electrically conductive contacts disposed on the face surface, and a plurality of side surfaces which define the outer perimeter of the semiconductor chip;
- IV. adhering the face surface of the semiconductor chip to the compliant layer;
- V. providing an expander ring having a plurality of inner side walls which define a central opening;
- VI. disposing the expander ring over the top surface of the dielectric element such that the semiconductor chips is disposed within the central opening of the expander ring and a gap is formed between the outer perimeter of the semiconductor chips and the inner side walls of the expander ring;
- VII. forming at least one lead connecting the semiconductor chip to the dielectric element by connecting at least one contact on the face surface of the semiconductor chip to the contact-end of one of the traces;
- and
- VIII. encapsulating the semiconductor chip assemblies by filling the gap and open spaces between the dielectric element, the compliant layer, the semiconductor chip and the expander ring with a liquid composition which is curable to an encapsulant;
- wherein
- w≧{(CTEexpander ring−CTEchip)Xc}/{CTEencapsulant(1+2p)};
- where w is the width of the gap;
- CTEchip is the coefficient of thermal expansion of the semiconductor chips;
- CTEexpander ring is the coefficient of thermal expansion of the expander ring;
- Xc is the shortest distance between a point on the outer perimeter of the semiconductor chip and the center of the semiconductor chip;
- CTEencapsulant is the coefficient of thermal expansion of the encapsulant;
- and p is the Poisson ratio of the encapsulant.
14 more elements
Dependencies are inferred from the claim text.