US 6,309,912 B1Granted

Method of interconnecting an embedded integrated circuit

AssigneeMotorola, Inc.

InventorsWayne Wen-Haw Chiou, Douglas H. Weisman, Kenneth D. Cornett

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Abstract

A method of interconnecting electrical terminations (12) of an integrated circuit die (30) to corresponding circuit traces (22) of a circuit carrying substrate (20). The die is placed in a cavity (24) in the substrate such that the electrical terminations on the die are aligned with corresponding circuit traces on the substrate, and so that the surfaces of the die and substrate are coplanar. A film (40) is vacuum laminated over the substrate and the die with heat and pressure. The film is then heated so that it flows to fill the spaces (34) between the die and sidewalls of the cavity, and is then cured. Excess film is then removed everywhere except that which is in the space between the die and the cavity walls. Electrical interconnections (100) are then plated up between the terminations and the circuit traces to bridge the distance between the terminations and the circuit traces. These interconnections are plated directly on the surface of those portions of the laminated film that lie between the sides of the die and of the cavity.

Claims14

Dependent claims

A method of interconnecting electrical terminations of an integrated circuit die to corresponding circuit traces of a circuit carrying substrate, comprising the steps of:

forming a cavity in the circuit carrying substrate, said cavity having a depth approximately equivalent to the thickness of the integrated circuit die and a length and width approximately equivalent to the length and width of the integrated circuit die;
placing the integrated circuit die in the cavity such that the electrical terminations are aligned with the corresponding circuit traces, and such that an upper surface of the die is substantially coplanar with an upper surface of the substrate;
laminating a film to the upper surfaces of the substrate and the die with heat and pressure while maintaining a vacuum on the workpieces;
heating the laminated film at a temperature sufficient to cause it to at least partially flow into any apertures between sides of the die and sidewalls of the cavity, and further heating at a temperature above the glass transition temperature of the film, sufficient to cure the film;
removing the film from the upper surfaces of the die and the substrate so as to expose the terminations and the circuit traces;
and
forming electrical interconnections between the terminations and the circuit traces, said electrical interconnections bridging the distance between the terminations and the circuit traces by being situated directly on the surface of those portions of the laminated film that lie between the sides of the die and sidewalls of the cavity.

4 more elements

A method of interconnecting electrical terminations of an integrated circuit die to corresponding circuit traces of a circuit carrying substrate, comprising the steps of:

forming a cavity in the circuit carrying substrate, said cavity having a depth approximately equivalent to the thickness of the integrated circuit die and a length and width approximately equivalent to the length and width of the integrated circuit die;
placing the integrated circuit die in the cavity such that the electrical terminations are aligned with the corresponding circuit traces, and such that an upper surface of the die is substantially coplanar with an upper surface of the substrate;
laminating a film to the upper surfaces of the substrate and the die with heat and pressure while maintaining a vacuum on the workpieces;
heating the laminated film at a temperature sufficient to planarize the film and cause it to at least partially flow into any apertures between sides of the die and sidewalls of the cavity, and further heating at a temperature above the glass transition temperature of the film, sufficient to cure the film;
removing the laminated film from the upper surfaces of the die and the substrate;
laminating a second film to the upper surfaces of the substrate and the die with heat and pressure while maintaining a vacuum on the workpieces;
photodefining vias in the second laminated film;
vacuum depositing a layer of titanium and a layer of copper over the second film and in the photodefined interconnection paths;
applying a layer of photoresist over the vacuum deposited metal;
photodefining interconnection paths between the terminations and the circuit traces in the layer of photoresist so as to reveal portions of the vacuum deposited metal;
electroplating copper onto the revealed portions of the vacuum deposited metal;
removing the layer of photoresist so as to reveal unplated portions of the vacuum deposited metal;
and
removing the revealed unplated portions of the vacuum deposited metal.

11 more elements

Dependencies are inferred from the claim text.