Method for power routing and distribution in an integrated circuit with multiple interconnect layers

A computer system programmed with a method for designing an integrated circuit which contains a plurality of high power logic cells, a plurality of low power logic cells and a plurality of interconnect layers, the method comprising the steps of:

• defining a power grid comprising a first plurality of power buses on a first interconnect layer oriented in a horizontal manner and a second plurality of power buses on a second interconnect layer oriented in a horizontal manner, such that the second plurality of buses are positioned approximately coincidentally with the first plurality of buses;
• placing a first portion of the plurality of low power logic cells and a first portion of the plurality of high power logic cells in a first horizontal row in such a manner that a position along the row of each low power logic cell and each high power logic cell is not constrained by a pre-positioned power via within the power grid;
• connecting each low power logic cell in the first portion of the plurality of low power logic cells to a first power bus in the first plurality of power buses on the first interconnect layer;
• and
• connecting each high power logic cell in the first portion of the plurality of high power logic cells to a second power bus in the second plurality of power buses on the second interconnect layer.

A mass storage device containing a program for a method for designing an integrated circuit which contains a plurality of high power logic cells, a plurality of low power logic cells and a plurality of interconnect layers, the method comprising the steps of:

• defining a power grid comprising a first plurality of power buses on a first interconnect layer oriented in a horizontal manner and a second plurality of power buses on a second interconnect layer oriented in a horizontal manner, such that the second plurality of buses are positioned approximately coincidentally with the first plurality of buses;
• placing a first portion of the plurality of low power logic cells and a first portion of the plurality of high power logic cells in a first horizontal row in such a manner that a position along the row of each low power logic cell and each high power logic cell is not constrained by a prepositioned power via within the power grid;
• connecting each low power logic cell in the first portion of the plurality of low power logic cells to a first power bus in the first plurality of power buses on the first interconnect layer;
• and
• connecting each high power logic cell in the first portion of the plurality of high power logic cells to a second power bus in the second plurality of power buses on the second interconnect layer.

A method for designing an integrated circuit which contains a plurality of high power logic cells, a plurality of low power logic cells and a plurality of interconnect layers, the method comprising the steps of:

• defining a power grid comprising a first plurality of power buses on a first interconnect layer oriented in a horizontal manner and a second plurality of power buses on a second interconnect layer oriented in a horizontal manner such that the second plurality of buses are positioned approximately coincidentally with the first plurality of buses;
• selecting the plurality of low power logic cells and the plurality of high power logic cells from a cell library which has a plurality of types of logic cells, wherein each high power logic cell includes an L1-L2 power via for connecting directly between one of the plurality of power buses on the first interconnect layer and a coincident one of the plurality of power buses on the second interconnect layer;
• placing a first portion of the plurality of low power logic cells and a first portion of the plurality of high power logic cells in a first horizontal row in such a manner that a position along the row of each low power logic cell and each high power logic cell is not constrained by a pre-positioned power via within the power grid;
• connecting each low power logic cell in the first portion of the plurality of low power logic cells to a first power bus in the first plurality of power buses on the first interconnect layer;
• and
• connecting the L1-L2 power via of each high power logic cell in the first portion of the high power logic cells to the first power bus and to a coincident power bus in the second plurality of power buses on the second interconnect layer.

An integrated circuit, comprising:

• a semiconductor substrate with a plurality of lower power logic cells and a plurality of higher power logic cells arranged therein in a plurality of rows oriented in a horizontal manner;
• a first interconnect layer disposed over the semiconductor substrate with a first plurality of power buses oriented in a horizontal manner therein, wherein each of the plurality of lower power logic cells has a power terminal connected to the first plurality of power buses and each of the plurality of higher power logic cells has a power terminal connected to the first plurality of power buses;
• a second interconnect layer and a third interconnect layer disposed consecutively over the first interconnect layer with signal lines therein interconnecting the plurality of lower power logic cells and the plurality of higher power logic cells;
• a fourth interconnect layer disposed over the third interconnect layer with a second plurality of power buses oriented in a horizontal manner therein, such that the second plurality of power buses are positioned approximately coincidentally with the first plurality of power buses;
• wherein a separate M1-M4 via connecting between one of the first plurality of power buses and a coincident one of the second plurality of power buses is located within the boundary of each of the plurality of higher power logic cells and connected to the power terminal of the respective higher power logic cell;
• and
• a fifth interconnect layer disposed over the third interconnect layer with a third plurality of power buses oriented in a vertical manner therein.