Method and apparatus for realizable interconnect reduction for on-chip RC circuits
AssigneeInternational Business Machines Corporation
InventorsAnirudh Devgan, Peter Redmond O'Brien
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AssigneeInternational Business Machines Corporation
InventorsAnirudh Devgan, Peter Redmond O'Brien
Estimating the term…
Realizable interconnect reduction techniques for on-chip RC interconnects are disclosed by first partitioning the original circuit into sets of two-port circuits to maintain the spatial sparsity of the reduced model. Each original two-port circuit is matched to a reduced RC circuit having a specific configuration. The moments of the original two-port circuits are calculated. Closed form expression values of the reduced circuit elements are then calculated from the moments of the original circuits. The closed form expressions for calculating the values of the elements in the reduced circuit use a reduced number of independent variables associated with the elements, thus simplifying the calculations. An efficient linear time moment computation technique is used for computing the moments for the two-port circuits.
A data processing system implemented method for realizing an interconnect reduction circuit for RC interconnects, the method comprising:
A data processing system implemented method for performing a circuit simulation by realizing an interconnect reduction circuit for simulating RC interconnect circuits, the method comprising:
A data processing system for realizing an interconnect reduction circuit for RC interconnects, the method comprising:
A data processing system for performing a circuit simulation by realizing an interconnect reduction circuit for simulating RC interconnect circuits, the method comprising:
A computer program product for realizing an interconnect reduction circuit for RC interconnects, the computer program product embodied on a computer readable medium and comprised of instructions, the instructions comprising:
A computer program product for performing a circuit simulation by realizing an interconnect reduction circuit for simulating RC interconnect circuits, the computer program product embodied on a computer readable medium and comprised of instructions, the instructions comprising:
Dependencies are inferred from the claim text.