Back to results
US 6,308,302 B1Granted
Semiconductor wiring technique for reducing electromigration
AssigneeInternational Business Machines Corporation
InventorsDavid James Hathaway, Douglas Wayne Kemerer, William John Livingstone, Daniel Joseph Mainiero, Joseph Leonard Metz, Jeannie Therese Harrigan Panner
Life of this patent
Estimating the term…
Abstract
An integrated circuit chip having at least one source pin and a plurality of sink pins. A wire segment connects the source pin to at least one of the sink pins and includes at least two segments where one of the segments is larger than the other where electromigration is likely to occur.
Claims4
An integrated circuit chip comprising:
- at least one source pin;
- a plurality of sink pins;
- a wire segment connecting the source pin to at least one of the sink pins, the wire segment being substantially straight and having at least one portion that is wider than the remaining portions where electromigration is likely to occur.
An integrated circuit chip comprising:
- a plurality of pins;
- a first wire segment coupling a first one of the pins to a second one of the pins, the first wire segment having a portion that is wider than the remaining portions where electromigration is likely to occur;
- and
- a second wire segment coupled to a third one of the pins and intersecting the first wire segment at the wider portion, a portion of the second wire segment being wider than the remaining portion where electromigration is likely to occur.
1 more element
Dependencies are inferred from the claim text.