Method and system for combinational verification having tight integration of verification techniques
AssigneeCadence Design Systems, Inc.
InventorsJerry R. Burch, Vigyan Singhal
Life of this patent
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AssigneeCadence Design Systems, Inc.
InventorsJerry R. Burch, Vigyan Singhal
Estimating the term…
A method and system for combinational verification tightly integrates multiple verification methods. The present invention performs random simulation on the inputs of two combinational netlists. The nets within the netlists are described as BDDs and divided into classes of cutpoint candidates based upon the signatures produced by the random simulation. Cutpoint candidates within each class are resolved to determine whether the candidates are equivalent. If the nets are likely to be equivalent, BDD composition is performed on the nets. Otherwise, SAT-based analysis is performed on the nets. If either method fails to resolve the cutpoints within an allocated amount of time or resources, then the other method is invoked and information learned by the first method is passed to the second method to assist in the resolution. This process repeats until the cutpoint candidates are resolved. If the cutpoint resolution produces a true negative, then the candidate classes are refined by performing directed simulation on the inputs of the netlists using the witness to the true negative generated by the cutpoint resolution. This directed simulation produces new candidate classes that are resolved as described above. If, after the cutpoint classes are refined, the outputs are in a different class, then the netlists are unequal. If a false negative is found after the cutpoints are resolved, a new cutpoint is created. If the outputs are in the current class, then the two netlists are equal. Otherwise, the cutpoints are further resolved as described above.
A method of determining whether first and second netlists stored in a memory of a computer system are equivalent, the method comprising the steps of:
A computer-readable medium having computer instructions stored thereon for causing a processor performing a series of acts to determine whether first and second combinational netlists comprised of a plurality of nets and stored in a memory of a computer system are equivalent, the series of acts comprising:
A computer system for performing combinational verification of first and second netlists each comprising of a plurality of nets and stored in a memory of the computer system, the computer system comprising:
A method of performing satisfiability analysis on a set of m root and p cutpoint BDDs representing a pair of cutpoint candidate BDDs stored in a memory of a computer system to determine whether the pair of cutpoint candidate BDDs are equivalent, the method comprising the steps of:
A method of determining whether a first netlist and a second netlist stored in a memory of a computer system are equivalent, the method comprising the steps of:
A computer system for performing combinational verification of a first netlist and a second netlist, each comprising a plurality of nets and stored in a memory of the computer system, the computer system comprising:
Dependencies are inferred from the claim text.