Parallel spectral reed-solomon encoder and decoder
AssigneeArizona Board of Regents
InventorsSatish Sridharan, Mark A. Neifeld
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Abstract
In the disclosed error correcting scheme, information data is encoded and decoded in parallel and in the spectral or frequency domains based on a Reed-Solomon (RS) code. As a result, when compared with space domain decoding, the spectral decoding scheme of the present invention shifts some of the computationally intensive modules into the encoder thus reducing decoder complexity. Thus, integrated circuit implementations of the error correcting scheme of the present invention are faster, have reduced power dissipation and occupy less chip area than serial encoders and decoders.
Claims14
An encoding/decoding system, comprising:
- a first integrated circuit including an encoder circuit symbols in response to second selected symbols of said spectral domain data and said plurality of error coefficients;
- and
- a comparison circuit comparing said error symbols with said spectral domain symbols to obtain said user information data as a result of said comparison.
An integrated circuit including a decoder circuit configured to correct errors present in Reed-Solomon encoded data and decoding said encoded data to output user information data, said decoder circuit comprising:
- a spectral domain transforming circuit transforming said Reed-Solomon encoded data into parallel spectral domain data, said parallel spectral domain data comprising a plurality of spectral domain symbols;
- an error signal generating circuit coupled to said inverse spectral domain transforming circuit, said error signal generating circuit outputting a plurality of error symbols in response to said parallel spectral domain symbols, said error signal generating circuit further comprising:
- a Berlekamp algorithm circuit acting on parallel first selected symbols of said spectral domain symbols to output a plurality of error coefficients in parallel, said Berlekamp algorithm circuit including at least t stages, where 2t=n−k, n being a number of symbols in a code word generated by said encoding circuit and k being a number of information symbols, each of said stages being spaced from one another and outputting a corresponding one of a term of an error locator polynomial;
- and
- a recursive extension circuit acting on said plurality of parallel error coefficients and second parallel selected symbols of said spectral domain data to output said error symbols;
- and
- a comparison circuit comparing said error symbols with said spectral domain symbols to obtain said user information data as a result of said comparison.
Dependencies are inferred from the claim text.