System for synchronizing discrete components to a common clock source
AssigneeHughes Electronics Corporation
InventorsKuriacose Joseph, Scott Casavant
Life of this patent
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Abstract
A method and apparatus for synchronizing downstream circuit boards with the clock values transmitted in the incoming bitstream of a digital broadcast data signal from a digital satellite system (DSS) or digital video broadcast (DVB) is disclosed. The disclosed embodiments use the generation of quasi-periodic interrupts which latch, at the same time for all downstream circuits, local clock times. The differences between successive local clock times are compared in downstream processors to differences between a front-end circuits locked system times to determine local clock adjustment values to synchronize downstream circuits.
Claims16
A method of synchronizing a plurality of computer subsystems to a transmitted clock in an incoming bitstream, wherein each subsystem comprises a local clock, the method comprising the steps of:
- locking said local clock of a front-end computer subsystem with said transmitted clock received in said incoming bitstream;
- and
- recording a plurality of quasi-periodic local times on said front-end computer subsystem and on each one of said plurality of downstream computer subsystems;
- and
- comparing each one of a plurality of quasi-periodic local times of said front-end computer subsystem with each one of said plurality of quasi-periodic local times of said plurality of downstream computer subsystems to determine synchronization;
- and
- adjusting said local clocks of each one of said plurality of downstream computer subsystems.
An apparatus for synchronizing a plurality of downstream computer subsystems to a transmitted clock of an incoming bitstream, wherein each one of said plurality of downstream computer subsystems comprises at least one clocking means for measuring a plurality of local timing values, said apparatus comprising:
- a computer comprising a motherboard, wherein a frontend computer subsystem and said plurality of downstream computer subsystems are connected to said motherboard;
- a front-end computer subsystem, wherein said front-end computer subsystem comprises a local clock and means to lock said local clock to said transmitted clock of said incoming bitstream;
- means for generating a plurality of quasi-periodic interrupts;
- means for transmitting said plurality of quasi-periodic interrupts to said front-end computer subsystem and to said plurality of downstream computer subsystems, wherein each one of said plurality of quasi-periodic interrupts arrives to said front-end computer subsystem and to each one of said plurality of downstream computer subsystems at the same time;
- means for storing a local time on said front-end computer subsystem and each one of said plurality of downstream computer subsystems, wherein said local time corresponds to each one of said plurality of quasi-periodic source interrupts;
- means for comparing the difference between successive values of a plurality of system times of said front-end computer subsystem with the difference between successive values of a plurality of quasi-periodic local times of said plurality of downstream computer subsystems;
- and
- means for adjusting said local clocks of each unsynchronized one of said plurality of downstream computer subsystems.
Dependencies are inferred from the claim text.